2011-05-16 06:08:42     implementing a "ring-buffer" structure with dma

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2011-05-16 06:08:42     implementing a "ring-buffer" structure with dma

Sebastian Heinrich (GERMANY)

Message: 100666   




I have an ADC connected to the BF537E through the PPI-Bus. The question is:


I want to use the ADC in a way that it writes continuously samples in the ram and on a signal (maybe i can use one of the framesyncs for that, even if they are designed to indicate a transfer.) it stops. Like an oscilloscope is able to do. My idea is know to implement a driver that works similar to the existing ppi driver except for the point that i don't want to give a count of samples. Then the driver should use DMA in a "ring-buffer" way. Write samples into the ram and if the ram is full, begin at the starting address again.


Is that even possible with the blackfin cpu ? Is there maybe a driver that does excactly what I want ?


Or is there maybe an other idea to implement the functionality i want ?




With best regards




Sebastian Heinrich




2011-05-16 09:18:29     implementing a "ring-buffer" structure with dma

Wojtek Skulski (UNITED STATES)

Message: 100667    Sebastian:


what is your sampling rate?




2011-05-16 09:53:14     Re: implementing a "ring-buffer" structure with dma

Sebastian Heinrich (GERMANY)

Message: 100669   


That depends on what frequency the user applies to the adc. The adc gets the sampling frequency from a dds-ic.


In maximum 25 MSample/second. This is working very good until now. If that high sample rate is not working with a "ring-buffer" structure, half of it would stiff be satisfying. But what has the sample rate to do with suhc a structure I want to implement ??


Isn't it a question of implementing a driver to use the correct dma-mode ??


Thanks for your help




2011-05-16 10:33:06     Re: implementing a "ring-buffer" structure withdma

Wojtek Skulski (UNITED STATES)

Message: 100670    Sebastian:


my question about frequency was out of curiosity. I have developed a

whole bunch of waveform digitizing hardware described on the website

  www.skutek.com. I always used FPGAs to capture and preprocess the

waveforms. The FPGAs are very good at continously capturing and

preprocessing data at high speed. The Blackfin is only doing

readout and post-processing. In such a way I can achieve continuous

operation of ten parallel ADC channels at 100 MSPS.


Your requirements may be different. I was just curious how fast you can go

without the FPGA. -- Wojtek




2011-05-16 11:35:53     Re: implementing a "ring-buffer" structure withdma

Sebastian Heinrich (GERMANY)

Message: 100673   


The requirements come from the Sweep-Frequency-Response-Analysis (SFRA) for transformers. There, the needed maximum frequency is around 4MHz - 5MHz. And, unfortunately, I did not design the originally system. I do only some rework to improve the performance.


For my bachelor-thesis I did some synchronisation stuff for a measurement plattform, designed to survey a 25GS/s DAC. This system had a Virtex4 as FPGA Plattform. So I do know the possibility to work with an FPGA, but thats simply not necessary in this case. I think the maximum speed is around the maximum clk-frequency of the ppi. If you can find an ADC converting that fast.


Do you know something about my original question ? :-)




2011-05-16 11:51:14     Re: implementing a "ring-buffer" structurewithdma

Wojtek Skulski (UNITED STATES)

Message: 100675    Sebastian:


> Do you know something about my original question ? :-)


Not yet ;-) Actually, using PPI to transfer data from the FPGA to the

BF561 is on my "to do" list. But somehow this list keeps growing rather

than shrinking ;-( So I am not there yet.


> If you can find an ADC converting that fast.


You mean 25 GSPS? Oh, well. I have it on my "to do" list. Probably around

the turn of this century I will get to this kind of speed. I firmly

believe that Blackfin++ BF56000 will run at 100 GHz. I will connect it to

the 25 GSPS chip and off we go.




2011-05-17 04:13:40     Re: implementing a "ring-buffer" structurewithdma

Sebastian Heinrich (GERMANY)

Message: 100689   


No I didn't mean 25Gs/s :-) Thats very fast and the project I was working with was at research status :-) (nevertheless the FPGA Board had 12,5Gbit/s Rocket IO's and coupling two ports together 25GS/s is not out of scope :-)


With "that fast" I meant a ADC that is as fast as the PPI bus is. If I remember right thats around 60MHz.


Back to topic:


I have seen now that the DMA provides an autobuffer mode that does the memory structure as I want it to be.


So I will try to write a PPI driver that uses the DMA in this mode and stop it if an irq comes.


The "normal" use of the ppi is working already. But I want to get a "history" on trigger event and not starting to measure.