2011-04-05 03:44:34     ICHACHE on SMP on BF561 EZKIT with 2010R5

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2011-04-05 03:44:34     ICHACHE on SMP on BF561 EZKIT with 2010R5

Alf Nilsson (SWEDEN)

Message: 99591   

 

Hi,

 

Does anyone know if ICACHE and DCACHE are functional when using SMP?

 

Because when I check cpuinfo, I get the following information.

 

root:/> cat proc/cpuinfo

 

processor       : 0

 

vendor_id       : Analog Devices

cpu family      : 0x27bb

model name      : ADSP-BF561 600(MHz CCLK) 100(MHz SCLK) (mpu off)

stepping        : 5 (Compiled for Rev 3)

cpu MHz         : 600.000/100.000

bogomips        : 2113.53

Calibration     : 1056768000 loops

cache size      : 16 KB(L1 icache) 32 KB(L1 dcache) 0 KB(L2 cache)

dbank-A/B       : cache/cache

external memory : cacheable in instruction cache

external memory : cacheable (write-through) in data cache

icache setup    : 4 Sub-banks/4 Ways, 32 Lines/Way

dcache setup    : 2 Super-banks/4 Sub-banks/2 Ways, 64 Lines/Way

SMP Dcache Flushes      : 11271

 

SMP Icache Flushes      : 0

 

processor       : 1

vendor_id       : Analog Devices

cpu family      : 0x27bb

model name      : ADSP-BF561 600(MHz CCLK) 100(MHz SCLK) (mpu off)

stepping        : 5 (Compiled for Rev 3)

cpu MHz         : 600.000/100.000

bogomips        : 2113.53

Calibration     : 1056768000 loops

cache size      : 0 KB(L1 icache) 0 KB(L1 dcache) 0 KB(L2 cache)

dbank-A/B       : sram/sram

external memory : cacheable in instruction cache

external memory : cacheable (write-through) in data cache

icache setup    : off

dcache setup    : 0 Super-banks/4 Sub-banks/2 Ways, 64 Lines/Way

SMP Dcache Flushes      : 11804

 

SMP Icache Flushes      : 0

 

L2 SRAM         : 128KB

L2 SRAM         : uncacheable in instruction cache

L2 SRAM         : uncacheable in data cache

board name      : ADI BF561-EZKIT

board memory    : 65536 kB (0x(null) -> 0x04000000)

kernel memory   : 57340 kB (0x00001000 -> 0x03800000)

 

Which makes it look like ICACHE and DCACHE are only available on core 0.

 

Any ideas or suggestions?

 

Cheers,

 

Alf

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2011-04-05 11:21:30     Re: ICHACHE on SMP on BF561 EZKIT with 2010R5

Mike Frysinger (UNITED STATES)

Message: 99608   

 

the cache is fine.  looks like we simply dont init the settings for the 2nd core and so it displays incorrectly.

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2011-04-13 16:48:17     Re: ICHACHE on SMP on BF561 EZKIT with 2010R5

Mike Frysinger (UNITED STATES)

Message: 99821   

 

btw, you can verify this behavior on your board by doing:

# cd /sys/kernel/debug/blackfin/mmu

# taskset 1 grep . *MEM_CONTROL

DMEM_CONTROL:0x0000300f

IMEM_CONTROL:0x00000007

# taskset 2 grep . *MEM_CONTROL

DMEM_CONTROL:0x0000300f

IMEM_CONTROL:0x00000007

 

or via jtag:

(gdb) thread 1

[Switching to thread 1 (Thread 1)]#0  0x0000dad4 in ?? ()

(gdb) mdl 0xFFE00004 1

0xffe00004:     0x0000300f

(gdb) mdl 0xFFE01004 1

0xffe01004:     0x00000007

(gdb) thread 2

[Switching to thread 2 (Thread 2)]#0  0x0000dad4 in ?? ()

(gdb) mdl 0xFFE00004 1

0xffe00004:     0x0000300f

(gdb) mdl 0xFFE01004 1

0xffe01004:     0x00000007

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2011-04-13 19:32:16     Re: ICHACHE on SMP on BF561 EZKIT with 2010R5

Mike Frysinger (UNITED STATES)

Message: 99824   

 

and this is fixed in trunk in svn rev 9830

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