2010-09-18 04:09:37     SDRAM CLOCK SUSPEND MODE

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2010-09-18 04:09:37     SDRAM CLOCK SUSPEND MODE

Usama Shakeel (PAKISTAN)

Message: 93599   

 

Hello,

 

 

 

I am using BF532 and SDRAM (MT48LC32), I want to share this Sdram between the FPGA and Blackfin. When I send a Bus Request signal to BF532 my uclinux hangs that means the Bus is granted to FPGA and when I remove the BR signal it resumes. But the clock is not suspended from BF532 to Sdram. Is there any configuration in uclinux which enables this as well. or any other way while staying on uclinux. I am using 2009 Dist.

 

 

 

Waiting for the response.

 

 

 

Regards

 

Usama Bin Shakeel

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2010-09-18 04:18:39     Re: SDRAM CLOCK SUSPEND MODE

Mike Frysinger (UNITED STATES)

Message: 93601   

 

if only one device may access the SDRAM at a time, and the FPGA is using the SDRAM, what do you expect ?  Linux is always going to require external memory access -- it is simply way too big to fit into internal memory.

 

most likely Linux isnt hanging ... the external memory request is.  hook JTAG up to the Blackfin and when it hangs, break in with JTAG to see what it is doing.  most likely, it is a load or store to the SDRAM.

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2010-09-18 04:59:11     Re: SDRAM CLOCK SUSPEND MODE

Usama Shakeel (PAKISTAN)

Message: 93603   

 

Yes Mike you are right .. but my question was is there a way that we can stop the clock being suplied by blackfin and leave the sdram in suspended clock mode.. As I saw through Logic probe that the clock is being supplied to sdram by Blackfin even after Bus grant to FPGA. I need to supply clock from FPGA so that I can read and write to SDRAM without sync issues...

 

 

 

Regards

 

Usama Bin Shakeel

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2010-09-18 05:29:25     Re: SDRAM CLOCK SUSPEND MODE

Mike Frysinger (UNITED STATES)

Message: 93608   

 

this is really a hardware issue and better asked here:

    ez.analog.com/

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