2010-08-19 09:56:58     Display driver blues (need 3 timers, and offset)...

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2010-08-19 09:56:58     Display driver blues (need 3 timers, and offset)...

Mark Urup (DENMARK)

Message: 92583   

 

Hi,

 

I'm trying to make a driver for a edt 2,8" display (ET028002DMU).

 

The display can run in both spi mode and ppi mode, and to get the best framerate, I want to use ppi mode.

 

My problem is that I need to use 3 timers. vsync, hsync and data-enable.

 

 

 

vsync and hsync I know how to program (they start at the same time), but the data-enable needs to go low 8 clks after each sync signal, and go high 8 clks  before the next sync.

 

My PWM periods and pulses should look something like this:

 

     ________________________________________________

__|                                                                                                                 vsync

 

      ________    ________     ________     ________    ________   _

__|                  |_|                  |_|                  |_|                  |_|                  |_|  hsync

 

          _____        ______        ______          ______       ______           _

____|           |___|             |___|             |____|            |___|             |____|  data-enable

 

 

 

Either I need to program a offset into the data-enable timer, center my pulse or use some gates and NOR/AND two timer signals together.

 

As far as I can tell from the BF522 HRM if I want to center the pulse (page 402) I need to do this in software, using interrupts (and i really don't want to do that)

The HRM does not mention anything about offsetting a timer, so I'm left with the NOR/AND gate solution.

 

 

 

Is this really true?

 

Regards

Mark Urup

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2010-08-19 10:18:10     Display driver blues (need 3 timers, andoffset)...

Michael Hennerich (GERMANY)

Message: 92585    The gate solution is probably the most reliable.

When offsetting timers you can try following:

 

1)Disable interrupts

2)Start the timers that need to run first

3)Read the timer counter resister in a tight loop and wait for the offset to arrive

4)Immediately start the remaining timers

5)Place a SSYNC(); right after the enable

6)Enable interrupts

 

-Michael

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2010-08-23 07:43:23     Re: Display driver blues (need 3 timers, andoffset)...

Mark Urup (DENMARK)

Message: 92691   

 

Thanks,

 

I now have a new problem offsetting the timers (I found out that I had no more timer pins let to use).

 

 

 

My code looks like this:

 

unsigned long flags;

 

local_irq_save(flags); //Disable interrupt handling

 

unsigned int reg = bfin_read32(TIMER_ENABLE_REGISTER);

 

enable_gptimers(TIMER_VSYNCbit | TIMER_HSYNCbit);

SSYNC();

 

//Wait for hsync offset (at THP+THB)

while(bfin_read_TIMER0_COUNTER() <= (THP+THB)) {

// while(get_gptimer_count(TIMER_HSYNC_id) < (THP+THB)) {

 

};

bfin_write32(TIMER_ENABLE_REGISTER, 0xff); //TODO: Only enable correct register

SSYNC();

// enable_gptimers(TIMER_DATAENABLE_HSYNC_bit);

 

//Wait for vsync offset (at TVP+TVB)

// while(bfin_read_TIMER1_COUNTER() <= (TVP+TVB)*TH) {

//// while(get_gptimer_count(TIMER_VSYNC_id) < (TVP+TVB)*TH) {

// };

//// bfin_write32(TIMER_ENABLE_REGISTER, 0x2 | reg);

// enable_gptimers(TIMER_DATAENABLE_VSYNC_bit);

 

disable_gptimers(TIMER_VSYNCbit | TIMER_HSYNCbit | TIMER_DATAENABLE_HSYNC_bit | TIMER_DATAENABLE_VSYNC_bit);

 

printk("HSYNC %d\n",get_gptimer_count(TIMER_HSYNC_id));

printk("VSYNC %d\n", get_gptimer_count(TIMER_VSYNC_id));

 

printk("HSYNC_DE %d\n", get_gptimer_count(TIMER_DATAENABLE_HSYNC_id));

printk("VSYNC_DE %d\n", get_gptimer_count(TIMER_DATAENABLE_VSYNC_id));

 

local_irq_restore(flags); //Restore interrupt handling

 

 

 

The problem is that the offset between HSYNC and HSYNC_DE isn't always the same :-(

 

I also found out that using the gptimers framework, the difference between HSYNC and HSYNC_DE both differs more, and the latency is bigger.

 

Additional info:

It's a BF526 (rev. 0.2) that runs at 300Mhz core and 100Mhz bus clock.

 

The PPI clock, which the timers run after, runs at 12Mhz.

The above code works fine up to about 8Mhz, but above that the offset is off by some clocks.

 

Do I need to disable the interrupts in another way?

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2010-08-31 08:38:21     Re: Display driver blues (need 3 timers, andoffset)...

Phil Wilshire (UNITED STATES)

Message: 92963   

 

Mark,

 

I solved a problem like this before by using additional ppi output lines for sync pulses.

 

I then embedded the sync pulses in the extra data lines.

 

I was able to get the specific wave form I needed in this manner.

 

 

 

Regards

 

Phil Wilshire

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