2010-07-09 10:40:23     Don't configure SPORT in TDM mode

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2010-07-09 10:40:23     Don't configure SPORT in TDM mode

Michail Kurochkin (BELARUS)

Message: 91107   

 

I attemt to configure SPORT0 in TDM mode.

I don't view clock signal on TSCLK0 or TFS0.

Can I view clock signal while no transfer data? If no, then how configure it?

 

#define TDM_FREQ 6144000 //TSCLK frequency HZ

#define TDM_FRAME_SYNC 8000 //Frame synchronize HZ

 

bfin_write_PORTF_MUX((bfin_read_PORTF_MUX() & ~3) | 1); // Select 2nd port F mux function

bfin_write_PORTF_FER( bfin_read_PORTF_FER() | PF4 | PF5); // Enable TSCLK0 and TFS0

 

SSYNC();

 

bfin_write_SPORT0_TCLKDIV((get_sclk() / 2 - 1) / TDM_FREQ); // Set devisor for TSCLK

bfin_write_SPORT0_TFSDIV(TDM_FREQ / (TDM_FRAME_SYNC + 1)); // Set devisor for TFS0

 

bfin_write_SPORT0_TCR1(TFSR | DITFS | ITFS | ITCLK); // Confugure SPORT0 in TDM mode

bfin_write_SPORT0_TCR2(0x7); // Set word length

bfin_write16(SPORT0_MCMC2, MCMEN); // Enable TDM mode

 

SSYNC();

bfin_write_SPORT0_TCR1(bfin_read_SPORT0_TCR1() | TSPEN); //Enable SPORT

SSYNC();

 

Why is don't work ?

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2010-07-09 12:22:25     Re: Don't configure SPORT in TDM mode

Mike Frysinger (UNITED STATES)

Message: 91109   

 

use the portmux functions to take care of pin mapping ... dont write PORTF_* MMRs directly

 

https://docs.blackfin.uclinux.org/doku.php?id=portmux

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2010-07-12 11:20:52     Re: Don't configure SPORT in TDM mode

Michail Kurochkin (BELARUS)

Message: 91172   

 

Mike, thanks for reply.

 

This code also not worked. Clock signal on TSCLK0 or TFS0 is not found.

 

#define TDM_FREQ 6144000 //TSCLK frequency HZ

#define TDM_FRAME_SYNC 8000 //Frame synchronize HZ

const unsigned short g_sport_pins[] = { P_SPORT0_TFS, P_SPORT0_TSCLK, P_SPORT0_DTPRI, P_SPORT0_DTSEC, 0 };

 

 

if(peripheral_request_list(g_sport_pins, "xxx"))

{

     printk("Can not request SPORT pins\n");

     return 1;

}

 

SSYNC();

 

bfin_write_SPORT0_TCLKDIV((get_sclk() / 2 - 1) / TDM_FREQ); // Set devisor for TSCLK

bfin_write_SPORT0_TFSDIV(TDM_FREQ / (TDM_FRAME_SYNC + 1)); // Set devisor for TFS0

 

bfin_write_SPORT0_TCR1(TFSR | DITFS | ITFS | ITCLK); // Confugure SPORT0 in TDM mode

bfin_write_SPORT0_TCR2(0x7); // Set word length

bfin_write16(SPORT0_MCMC2, MCMEN); // Enable TDM mode

 

SSYNC();

bfin_write_SPORT0_TCR1(bfin_read_SPORT0_TCR1() | TSPEN); //Enable SPORT

SSYNC();

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2010-07-13 04:50:24     Re: Don't configure SPORT in TDM mode

Mike Sinkovsky (RUSSIAN FEDERATION)

Message: 91193   

 

Michail, там еще некоторые регистры нужно инициализировать для многоканального режима

 

У меня инициализатор такой:

 

struct sport {

    struct sport_register *regs;

    int dma_rx;

    int dma_tx;

    int irq_mode;

    int frame_delay;

};

 

void sport_configure(struct sport *sport)

{

    struct sport_register *regs = sport->regs;

    int dma_rx = sport->dma_rx;

    int dma_tx = sport->dma_tx;

    ulong sclk = get_sclk();

 

    memset(sport->dma_buffer, 0xD5, SPORT_SLOTS * DAHDI_CHUNKSIZE * 2);

 

    /* Disable SPORT before init */

    regs->rcr1 = 0;

    regs->rcr2 = 0;

    regs->tcr1 = 0;

    regs->tcr2 = 0;

    SSYNC();

 

    /* Set channels Tx */

    regs->mtcs0 = SPORT_MASK0;

    regs->mtcs1 = SPORT_MASK1;

    regs->mtcs2 = SPORT_MASK2;

    regs->mtcs3 = SPORT_MASK3;

 

    /* Set channels Rx */

    regs->mrcs0 = SPORT_MASK0;

    regs->mrcs1 = SPORT_MASK1;

    regs->mrcs2 = SPORT_MASK2;

    regs->mrcs3 = SPORT_MASK3;

 

    /* Transmit and Receive Configuration */

    regs->tclkdiv = (sclk / (32 * 64000) / 2) - 1;

    regs->rclkdiv = (sclk / (32 * 64000) / 2) - 1;

    regs->tfsdiv = (32 * 8) - 1;

    regs->rfsdiv = (32 * 8) - 1;

 

    /* Transmit and Receive Configuration */

    regs->rcr1 = RFSR; /* Rx Frame Sync Required */

    regs->tcr1 = TFSR; /* Tx Frame Sync Required */

    regs->rcr2 = RXSE | 7;

    regs->tcr2 = TXSE | 7;

 

    /* Set SPORT in Multichannel mode */

    regs->mcmc1 = 0x3000; /* Window Size = 32, Offset = 0 */

    regs->mcmc2 = ((sport->frame_delay & 1) << 12) /* Frame Delay*/

          | MCDTXPE /* Multichannel DMA Transmit Packing */

          | MCDRXPE /* Multichannel DMA Receive Packing */

          | MCMEN; /* Multichannel Frame Mode Enable */

    SSYNC();

 

    set_dma_start_addr(dma_tx, (unsigned long)(sport->dma_buffer));

    set_dma_x_count(dma_tx, SPORT_SLOTS * DAHDI_CHUNKSIZE);

    set_dma_x_modify(dma_tx, 1);

    set_dma_y_count(dma_tx, 2);

    set_dma_y_modify(dma_tx, 1);

    set_dma_config(dma_tx, set_bfin_dma_config(

          DIR_READ,

          DMA_FLOW_AUTO,

          INTR_DISABLE,

          DIMENSION_2D,

          DATA_SIZE_8,

          DMA_NOSYNC_KEEP_DMA_BUF));

 

    set_dma_start_addr(dma_rx, (unsigned long)(sport->dma_buffer +

          SPORT_SLOTS * DAHDI_CHUNKSIZE * 2));

    set_dma_x_count(dma_rx, SPORT_SLOTS * DAHDI_CHUNKSIZE);

    set_dma_x_modify(dma_rx, 1);

    set_dma_y_count(dma_rx, 2);

    set_dma_y_modify(dma_rx, 1);

    set_dma_config(dma_rx, set_bfin_dma_config(

         DIR_WRITE,

         DMA_FLOW_AUTO,

         sport->irq_mode,

         DIMENSION_2D,

         DATA_SIZE_8,

         DMA_NOSYNC_KEEP_DMA_BUF));

 

    SSYNC();

}

 

void sport_enable(struct sport *sport)

{

    enable_dma(sport->dma_tx);

    enable_dma(sport->dma_rx);

    sport->regs->tcr1 |= TSPEN;

    sport->regs->rcr1 |= RSPEN;

    SSYNC();

}

 

void sport_disable(struct sport *sport)

{

    sport->regs->tcr1 &= ~TSPEN;

    sport->regs->rcr1 &= ~RSPEN;

    SSYNC();

    disable_dma(sport->dma_tx);

    disable_dma(sport->dma_rx);

}

 

void sport_sync_internal(struct sport *sport)

{

    sport->regs->rcr1 = IRCLK | /* Internal RX Clock Select */

          IRFS | /* Internal RX Frame Sync Select */

          RFSR; /* Rx Frame Sync Required */

    sport->regs->tcr1 = ITCLK | /* Internal TX Clock Select */

          ITFS | /* Internal TX Frame Sync Select */

          TFSR; /* Tx Frame Sync Required */

}

 

void sport_sync_external(struct sport *sport)

{

    sport->regs->rcr1 = RFSR; /* Rx Frame Sync Required */

    sport->regs->tcr1 = TFSR; /* Tx Frame Sync Required */

}

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