2010-06-30 04:58:04     cpufreq and sysclkfreq BF537

Document created by Aaronwu Employee on Aug 22, 2013
Version 1Show Document
  • View in full screen mode

2010-06-30 04:58:04     cpufreq and sysclkfreq BF537

Patrick Hotz (GERMANY)

Message: 90768   




I´m currently trying the "cpufreq" on my BF537 CPU.


I have enabled the "CPU Frequency scaling" (uClinux-dist2009R1_RC4) and the "cpufreq-tools" in userspace.

I can set the CPU-Freq to 263MHz and 525Mhz (normally i use 525Mhz).

The SysClk is always 131,250Mhz.


In the datasheet there are some registers to set the PLL, Core Multiplier, Input divider and some other registers to set the Core and the SystemClk frequencies.


My question is following:

- Is it possible to set the CPU frequencies in several stages (maybe 150MHz till 525MHz in steps of 50Mhz) ?

- Is it possible to set the SysClk frequencies (fom 50Mhz till 131,250Mhz in several steps) ?




I know that the current driver only can set the CPU in two steps (min and max)....

maybe i can modify this driver..




Best regards,





2010-06-30 06:03:43     cpufreq and sysclkfreq BF537

Michael Hennerich (GERMANY)

Message: 90769    Take a look at the Blackfin Hardware Reference Manual (HRM)

For CCLK divide ratios (CSEL) down from VCO are 1,2,4,8

So in case your VCO runs at 525MHz then the options are

525MHz or 263MHz (525MHz/4 or 8).

On some Blackfin derivatives there are restrictions that CCLK must be > SCLK.


It's not recommended to change SCLK - since this would require to reprogram SDRAM timings as well as everything

else that depends on SCLK. Such as reprogram UART baud registers, etc.