2010-04-16 18:55:28     CPLB miss while booting

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2010-04-16 18:55:28     CPLB miss while booting

Bryan Hilterbrand (UNITED STATES)

Message: 88534   


I've inherited a project (with little documentation) from a contractor that we no longer use. The project uses a custom BF536 board running U-boot and uCLinux. We have a copy of the environment that the contractor used, and his last version runs just fine on our hardware, but the version I compile end up with a CPLB miss.


The first thing everyone is going to suggest is to upgrade to the latest version - my boss has specifically told me to stay on this version for now. I'd like to upgrade, but I can't. If anyone can help me figure out why this is happening, I would be very grateful!






$ bfin-linux-uclibc-gcc -v

Using built-in specs.

Target: bfin-linux-uclibc

Configured with: /home/nathan/lab/Kryptic/tools/bf-toolchain-e1.0/buildscript/../gcc-4.1/configure --build=i686-pc-linux-gnu --host=i686-pc-linux-gnu --target=bfin-linux-uclibc --prefix=/home/nathan/lab/Kryptic/tools/bf-toolchain-e1.0/buildscript/build-bfin-gcc-4.1/-linux-uclibc --enable-threads=posix --enable-shared --with-sysroot=/home/nathan/lab/Kryptic/tools/bf-toolchain-e1.0/buildscript/build-bfin-gcc-4.1/-linux-uclibc/bfin-linux-uclibc/runtime --disable-libstdcxx-pch --disable-symvers --disable-libssp --enable-version-specific-runtime-libs --enable-__cxa_atexit

Thread model: posix

gcc version 4.1.2 (ADI svn)




U-Boot-1.1.3-ADI-R06R2 (Mar  6 2009 - 12:23:26)


Firm:  Some Tech, Inc.

Board: Anigma GCMB

CPU:   ADSP BF536 Rev.: 0.3

Clock: VCO: 400 MHz, Core: 400 MHz, System: 80 MHz



In:    serial

Out:   serial

Err:   serial

Using MAC Address 00:24:35:00:00:89

Net:    ADI BF53X EMAC

I2C:   ready

Hit any key to stop autoboot:  0

## Booting image at 20020000 ...

   Image Name:   Linux-

   Created:      2010-04-15  23:38:56 UTC

   Image Type:   Blackfin Linux Kernel Image (gzip compressed)

   Data Size:    1004700 Bytes = 981.2 kB

   Load Address: 00001000

   Entry Point:  00001000

   Verifying Checksum ... OK

   Uncompressing Kernel Image ... OK

Starting Kernel at = 1000

Linux version (bhilterbrand@bh-ubuntu) (gcc version 4.1.

1 (ADI 06R2)) #212 Thu Apr 15 17:38:53 MDT 2010

Blackfin support (C) 2004-2006 Analog Devices, Inc.

Compiled for ADSP-BF536 Rev. 0.3

Blackfin uClinux support by   blackfin.uclinux.org/

Processor Speed: 400 MHz core clock and 80 Mhz System Clock

Board Memory: 16MB

Kernel Managed Memory: 16MB

Memory map:

  text      = 0x00001000-0x00168ba4

  init      = 0x00169000-0x001790cc

  data      = 0x0017b3f4-0x001c0b0c

  stack     = 0x0017c000-0x0017e000

  bss       = 0x001c0b10-0x001f0608

  available = 0x001f0608-0x00eff000

  DMA Zone  = 0x00f00000-0x01000000

Instruction Cache Enabled

Data Cache Enabled (write-through)

Hardware Trace Enabled

Built 1 zonelists.  Total pages: 3810

Kernel command line: root=/dev/mtdblock2 rw rootfstype=jffs2

Configuring Blackfin Priority Driven Interrupts

PID hash table entries: 64 (order: 6, 256 bytes)

I-pipe 1.6-02: pipeline enabled.

Dentry cache hash table entries: 2048 (order: 1, 8192 bytes)

Inode-cache hash table entries: 1024 (order: 0, 4096 bytes)

Physical pages: eff

Memory available: 13084k/14867k RAM, (64k init code, 1438k kernel code, 190k dat

a, 1024k dma)

Blackfin Scratchpad data SRAM: 4 KB

Blackfin Instruction SRAM: 48 KB

Security Framework v1.0.0 initialized

Capability LSM initialized

Mount-cache hash table entries: 512

NET: Registered protocol family 16

Blackfin GPIO Controller

Blackfin DMA Controller

gcmb_init(): registering device resources

Generic PHY: Registered new driver

NET: Registered protocol family 2

IP route cache hash table entries: 128 (order: -3, 512 bytes)

TCP established hash table entries: 512 (order: -1, 2048 bytes)

TCP bind hash table entries: 256 (order: -2, 1024 bytes)

TCP: Hash tables configured (established 512 bind 256)

TCP reno registered

I-pipe: Domain Xenomai registered.

Xenomai: hal/blackfin started.

Xenomai: real-time nucleus v2.3.1 (One Robot's Dream) loaded.

Xenomai: starting native API services.

Xenomai: starting POSIX services.

Xenomai: starting RTDM services.

JFFS2 version 2.2. (NAND) (C) 2001-2006 Red Hat, Inc.

io scheduler noop registered

io scheduler anticipatory registered (default)

io scheduler cfq registered

Dynamic Power Management Controller Driver v0.1: major=10, minor = 254

Register Bfin Processor Access Driver v0.0.5

Register Bfin Processor Access RTDM Driver v0.0.3

LCD: char device registered

LCD: char device added

LCD: init OK,  rows: 4, columns: 20

keypad: Copyright (C) 2000-2001, Greg Ungerer (gerg@snapgear.com)

2.6 Update and SoM support by EMAC.Inc->NZG 2005

Serial: Blackfin serial driver

bfin-uart.1: ttyBF0 at MMIO 0xffc00400 (irq = 18) is a BFIN-UART

RAMDISK driver initialized: 1 RAM disks of 4096K size 1024 blocksize

mmc version 1.0 loading

LXT970: Registered new driver

LXT971: Registered new driver

Blackfin mac net device registered

physmap platform flash device: 003c0000 at 20000000

physmap-flash.0: Found 1 x16 devices at 0x0 in 16-bit bank

NOR chip too large to fit in mapping. Attempting to cope...

Amd/Fujitsu Extended Query Table at 0x0040

number of CFI chips: 1

cfi_cmdset_0002: Disabling erase-suspend-program due to code brokenness.

Reducing visibility of 8192KiB chip to 3840KiB

RedBoot partition parsing not available

Using physmap partition information

Creating 3 MTD partitions on "physmap-flash.0":

0x00000000-0x00020000 : "Bootloader"

0x00020000-0x001c0000 : "Kernel"

0x001c0000-0x003c0000 : "JFFS2"

rtc-bfin rtc-bfin: rtc intf: sysfs

rtc-bfin rtc-bfin: rtc intf: proc

rtc-bfin rtc-bfin: rtc intf: dev (254:0)

rtc-bfin rtc-bfin: rtc core: registered rtc-bfin as rtc0

i2c /dev entries driver

Register LM73 Temperature Sensor Driver v1.0.6

Register LM73 RTDM Driver v0.0.2

Register SC16IS740/750/760 TWI UART Driver v1.0.8

Register TWI UART RTDM Driver v0.0.8

Register BMP085 Pressure Sensor Driver v1.2.0

BMP085 Sensor detected at address 0x77

Register BMP085 RTDM Driver v1.3.0

Registering BMP085 RTDM bmp085_0x77 at address 0x77

ecoreex version 1.2 loading

GCMB CPLD expansion R1.0 detected at 203f0000

registering GPIO class

registering gpo device: dlais321

registering gpio device: spi_7730

registering gpio device: spi_det

registering gpi device: rlwc3210

registering gpio device: lcd

registering gpi device: keypad

registering gpo device: xxxxxx54

registering gpo device: det_sel

registering gpi device: det_rdy

boardspec version 1.0 loading

registering gpo device: control_l

registering gpi device: status

registering gpo device: control_h

registering bf537 pwm device: prop_valve2

registering PWM class

registering bf537 pwm device: prop_valve1

registering bf537 pwm device: pump2

registering bf537 pwm device: pump1

registering bf537 pwm device: box_heaters

registering bf537 pwm device: trap_heater

registering gpio device: spi_3208

registering gpio device: peltier

registering gpio device: sd_card

TCP cubic registered

NET: Registered protocol family 1

NET: Registered protocol family 17

rtc-bfin rtc-bfin: setting the system clock to 2003-08-22 23:45:56 (1061595956)

VFS: Mounted root (jffs2 filesystem).

Freeing unused kernel memory: 64k freed (0x169000 - 0x178000)

dma_alloc_init: dma_page @ 0x00d16000 - 256 pages at 0x00f00000


Welcome to:

       ____ _  _

      /  __| ||_|             _  _

_   _| |  | | _ ____  _   _ \ \/ /

| | | | |  | || |  _Data access CPLB miss

- Used by the MMU to signal a CPLB miss on a data access.




COMM=boa PID=177

TEXT = 0x00d40000-0x00d50eec  DATA = 0x00d60eec-0x00d65b04

BSS = 0x00d65b04-0x00cc0000   USER-STACK = 0x00cdfea0


return address: 0x00d479be; contents of [PC-16...PC+8]:

0c00 187b 0c05 18af 0000 320d 9948 0c00

1881 e51a 017f 9110 4868 103c 320e 5e69 X

910e 0c06 3061 1407 2013 320e a088 0c00


RETE:  00000000  RETN: 00d6c000  RETX: 00d479be  RETS: 00d47c7e

IPEND: 0030  SYSCFG: 0036

SEQSTAT: 00000026    SP: 00d6bf24

R0: 00000000    R1: 2441739d    R2: 00cdf865    R3: 00000002

R4: 00cdf84c    R5: 00cdf84c    R6: 00d62e5c    R7: 00d618c8

P0: 00d618c8    P1: 91dbfcd0    P2: 00d62e20    P3: 00d618c8

P4: 00cdf865    P5: 2441739d    FP: 00cdf7f8

A0.w: 98af4925    A0.x: 00000000    A1.w: 000087d9    A1.x: 00000000

LB0: 0039d52b  LT0: 0039d52a  LC0: 00000000

LB1: 00c1a3d3  LT1: 00c1a3d2  LC1: 00000000

B0: 00000000  L0: 00000000  M0: 00000000  I0: 00cdf860

B1: 00000000  L1: 00000000  M1: 00000000  I1: 00001000

B2: 00000000  L2: 00000000  M2: 00000000  I2: 00000000

B3: 00000000  L3: 00000000  M3: 00000000  I3: 00000000


USP: 00cdf7e4   ASTAT: 02001024





Hardware Trace:

0 Target : <0x000044d0> { _trap_c + 0x0 }

   Source : <0xffa00ab4> { _exception_to_level5 + 0xb4 }

1 Target : <0xffa00a00> { _exception_to_level5 + 0x0 }

   Source : <0xffa009fe> { _ex_trap_c + 0x4e }

2 Target : <0xffa00958> { _handle_bad_cplb + 0x0 }

   Source : <0xffa0046c> { __cplb_hdr + 0x5c }

3 Target : <0xffa0046a> { __cplb_hdr + 0x5a }

   Source : <0x00004462> { _panic_cplb_error + 0x16 }

4 Target : <0x0000444c> { _panic_cplb_error + 0x0 }

   Source : <0xffa00466> { __cplb_hdr + 0x56 }

5 Target : <0xffa00462> { __cplb_hdr + 0x52 }

   Source : <0xffa00452> { __cplb_hdr + 0x42 }

6 Target : <0xffa0044c> { __cplb_hdr + 0x3c }

   Source : <0xffa00446> { __cplb_hdr + 0x36 }

7 Target : <0xffa00444> { __cplb_hdr + 0x34 }

   Source : <0xffa0043c> { __cplb_hdr + 0x2c }

8 Target : <0xffa00438> { __cplb_hdr + 0x28 }

   Source : <0xffa005b0> { _cplb_mgr + 0x140 }

9 Target : <0xffa005ac> { _cplb_mgr + 0x13c }

   Source : <0xffa00714> { _cplb_mgr + 0x2a4 }

10 Target : <0xffa0070c> { _cplb_mgr + 0x29c }

   Source : <0xffa00728> { _cplb_mgr + 0x2b8 }

11 Target : <0xffa0070c> { _cplb_mgr + 0x29c }

   Source : <0xffa00728> { _cplb_mgr + 0x2b8 }

12 Target : <0xffa0070c> { _cplb_mgr + 0x29c }

   Source : <0xffa00728> { _cplb_mgr + 0x2b8 }

13 Target : <0xffa0070c> { _cplb_mgr + 0x29c }

   Source : <0xffa00728> { _cplb_mgr + 0x2b8 }

14 Target : <0xffa0070c> { _cplb_mgr + 0x29c }

   Source : <0xffa00728> { _cplb_mgr + 0x2b8 }

15 Target : <0xffa0070c> { _cplb_mgr + 0x29c }

   Source : <0xffa00728> { _cplb_mgr + 0x2b8 }

Stack from 00d6bef8:

        ffa00cdc ffa00ab8 00180744 ffe02014 00180744 00180740 00cdf84c 00cdf84c

        00000100 00cdf84c 00001000 00d479be 00000030 00000026 00000000 00d6c000

        00d479be 00d479be 00d47c7e 00000000 02001024 00c1a3d3 0039d52b 00c1a3d2

        0039d52a 00000000 00000000 000087d9 00000000 98af4925 00000000 00000000

        00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000

        00000000 00000000 00000000 00000000 00000000 00001000 00cdf860 00cdf7e4

Call Trace:


\| | | | \  /

| |_| | |__| || | | | | |_| | /  \

|  ___\____|_||_|_| |_|\____|/_/\_\



For further information see:




177: Bus error




blackfin login:




2010-04-16 19:09:00     Re: CPLB miss while booting

Mike Frysinger (UNITED STATES)

Message: 88535   


it could be a bug in the kernel we fixed, or a bug in boa.  the crash is in boa, but you need to enable the kconfig option (CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE) to disable the tracebuffer while in the cplb miss code so that the trace reflects boa.


then you can use the documentation to find out what boa is doing wrong:





2010-04-18 01:38:19     Re: CPLB miss while booting


Message: 88550   




Have a converstation with your management about upgrading.


In 2006 - (the release you are using) - we did not know about lots of silicon problems that were discovered since then. Since 2007 (the latest changelog in the 537 anomaly sheet), the following anomalies were added (I know there were others, but this is the latest on the changelog). I would need to go back and dig up some older stuff to get the real details...


05000341       - Ethernet MAC MDIO Reads Do Not Meet IEEE Specification

05000357 (k)   - Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled

05000359       - DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked

05000350 (u)   - UART Gets Disabled after UART Boot

05000355       - Regulator Programming Blocked when Hibernate Wakeup Source Remains Active

05000366       - PPI Underflow Error Goes Undetected in ITU-R 656 Mode

05000371 (ukt) - Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration

05000402       - SSYNC Stalls Processor when Executed from Non-Cacheable Memory

05000403       - Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall

05000416 (k)   - Speculative Fetches Can Cause Undesired External FIFO Operations

05000425       - Multichannel SPORT Channel Misalignment Under Specific Configuration

05000426 (t)   - Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors


The (k) means a workaround exists in the current kernel. t means toolchain, and u means u-boot. More info can be found at:




0.3 silicon was not out when the 2006 release was made - no one has tested it. You may be the only person running that combination of hardware/software.


At a min - you need to go through the last three years of fixes to everything (including compiler) - and apply them to your own source if you want to stay with 2006.


If you need help upgrading - we can provide that - the scope depends on how competent your contractor was, and how many things they modified to get things going...






2010-04-20 12:11:42     Re: CPLB miss while booting

Bryan Hilterbrand (UNITED STATES)

Message: 88658   


Mike and Robin, thanks for the replies!


Robin, we're using the BF536 - do these anomolies still apply?


Mike, I tried to enable CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE, but I didn't see any difference in the error output. I'm going to make sure I put it in the right place and try again this morning.




2010-04-20 16:06:27     Re: CPLB miss while booting


Message: 88664   




Same applies to both 536 and 537.






2010-04-20 19:32:08     Re: CPLB miss while booting

Bryan Hilterbrand (UNITED STATES)

Message: 88676   


Mike, I'm a newbie to compiling the uClinux kernel. I found a config file down in the vendor directories that has that option, but that file says that it is generated. How do I get that option set?




2010-04-20 22:08:49     Re: CPLB miss while booting

Mike Frysinger (UNITED STATES)

Message: 88682   


you dont edit config files directly.  you use the configuration system to do things.


run `make menuconfig`.




2010-04-21 12:12:27     Re: CPLB miss while booting

Bryan Hilterbrand (UNITED STATES)

Message: 88729   


I tried 'make menuconfig' and I didn't see that option. There were so many options that it's possible I missed it, but I was pretty careful. Can you tell me which section that option is in? I'll take another look while I'm waiting for your reply.




2010-04-21 12:19:53     Re: CPLB miss while booting

Mike Frysinger (UNITED STATES)

Message: 88730   


it's under kernel debugging




2010-04-21 12:54:23     Re: CPLB miss while booting

Bryan Hilterbrand (UNITED STATES)

Message: 88731   


Mike, thanks for being patient with me. Here are the kernel debugging options (under kernel hacking) that come up for me:


[*] Kernel debugging

(14)  Kernel log buffer size (16 => 64KB, 17 => 128KB)

[*]   Detect Soft Lockups

[ ]   Collect scheduler statistics

[ ]   Debug slab memory allocations

[ ]   RT Mutex debugging, deadlock detection

[ ]   Built-in scriptable tester for rt-mutexes

[ ]   Spinlock and rw-lock debugging: basic checks

[ ]   Mutex debugging: basic checks

[ ]   RW-sem debugging: basic checks

[ ]   Spinlock debugging: sleep-inside-spinlock checking

[ ]   Locking API boot-time self-tests

[ ]   kobject debugging

[ ]   Verbose BUG() reporting (adds 70K)

[ ]   Compile the kernel with debug info


None of these look like the right option to me. Any thoughts?





2010-04-21 13:27:09     Re: CPLB miss while booting


Message: 88733   




Scroll down. If it is still not there - Have a look in your ./arch/blackfin/Kconfig.debug


If it doesn't look like:




specifically around lines 130 - you don't have 2008R1 either - you have 2007, or something inbetween.




2010-04-21 13:36:40     Re: CPLB miss while booting

Bryan Hilterbrand (UNITED STATES)

Message: 88735   


It is 2007R1:


## Booting image at 20020000 ...

   Image Name:   Linux-


Does this option exist in 2007R1?





2010-04-21 14:26:35     Re: CPLB miss while booting


Message: 88736   




It should be:




lines 935.


The option was added revision 2069, Sat Sep 2 01:26:23 2006






2010-04-22 21:09:38     Re: CPLB miss while booting

Bryan Hilterbrand (UNITED STATES)

Message: 88790   


Thanks Robin and Mike! We brought the contractor back for a little while, and we figured out that I was using the wrong toolchain - it was only one revision different (r2 instead of r1)! I'll be more careful to match the versions in the future.


Thanks for your suggestions - I learned a lot from your advice.