2010-03-17 11:50:17     TFT Driver with Hardware timer

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2010-03-17 11:50:17     TFT Driver with Hardware timer

Miquel Soler i Mir (SPAIN)

Message: 87335   

 

Hello.

 

I'm working with CM-BF537E + TFT_Board + Hitachitx09 using kernel version 2009R1-RC6 and toolchain version 2009R1-RC11.

 

I found one problem in TFT:  all the lines has one pixel shifted to right.

 

To check this error I connect a logic analyzer (LogicPort from intronix 500 MHz) to control the signals of the hardware timers (PPICLK + TMR0[HSYNC] + TMR1[DTMG] + TMR2[VSYNC]).

 

For my surprice I found that the TMR0 has a delay of 100 ns.

 

To check the error I modified the Hitachi-tx09.c driver to configure the timer TMR0, TMR1 and TMR2 identically.

 

The PPICLK is 125 MHz / 26 = 4.807.692 Hz (Period of 208 ns and duty cycle of 50 %)

 

The TMR0, TMR1 and TMR2 have the same configuration, the rest of the code is the same as the bluetechnix driver.

 

    /* dclk clock output */

    BFIN_WRITE(TIMER_DCLK, CONFIG) (PERIOD_CNT | PULSE_HI | PWM_OUT);

    timer_period = get_sclk() / (CONFIG_FB_HITACHI_TX09_REFRESHRATE * 89271);

    BFIN_WRITE(TIMER_DCLK, PERIOD) (timer_period);

    BFIN_WRITE(TIMER_DCLK, WIDTH) (timer_period / 2);

    SSYNC();

 

    /* hsync timer */

    BFIN_WRITE(TIMER_HSYNC, CONFIG) (CLK_SEL | TIN_SEL | PERIOD_CNT | PWM_OUT);    /* clocked by PPI_clk */

    BFIN_WRITE(TIMER_HSYNC, PERIOD) (273);    /* 240 + 33 blanking */

    BFIN_WRITE(TIMER_HSYNC, WIDTH) (10);

    SSYNC();

 

    /* dtmg timer */

    BFIN_WRITE(TIMER_DTMG, CONFIG) (CLK_SEL | TIN_SEL | PERIOD_CNT | PWM_OUT);    /* clocked by PPI_clk */

    BFIN_WRITE(TIMER_DTMG, PERIOD) (273);

    BFIN_WRITE(TIMER_DTMG, WIDTH) (10);

    SSYNC();

 

    /* vsync timer */

    BFIN_WRITE(TIMER_VSYNC, CONFIG) (CLK_SEL | TIN_SEL | PERIOD_CNT | PWM_OUT);    /* clocked by PPI_clk */

    BFIN_WRITE(TIMER_VSYNC, PERIOD) (273);

    BFIN_WRITE(TIMER_VSYNC, WIDTH) (10);

    SSYNC();

 

Checking with the logic analizer seems to be OK, but if you zoom in it shows that the TMR has a delay of 100 ns.

 

In the picture logic1.png seems to be all OK.

 

In the picture logic2.png you can see the error. The TMR0 has a delay of 104 ns from the rest, that is 1/2 of the PPICLK period.

 

The Timer TMR1 and TMR2 are activated by rising flag of PPICLK but it seems that the Timer TMR0 is activated by falling flag !!!!

 

The souce code to configure all the timer TMR0, TMR1 and TMR2 is the same (see above).

 

Any clue what goes wrong here?

 

Miquel

 

logic1.png

logic2.png

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2010-03-17 12:28:46     TFT Driver with Hardware timer

Michael Hennerich (GERMANY)

Message: 87337    We didn't write that driver -

But if you see a delay between two timers - and you doesn't like that -

Enable the timers simultaneously...

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2010-03-17 14:20:13     Re: TFT Driver with Hardware timer

Miquel Soler i Mir (SPAIN)

Message: 87342   

 

Thanks Michael

 

I think is not a problem of inicialization:

 

static void start_timers(void)

{

    unsigned long flags;

 

    local_irq_save(flags);

 

    bfin_write_TIMER_ENABLE((1 << TIMER_HSYNC) | (1 << TIMER_DTMG) | (1 << TIMER_VSYNC));

    SSYNC();

    bfin_write_TIMER_ENABLE(1 << TIMER_DCLK);

 

    SSYNC();

    mdelay(50);

    gpio_set_value(PCI_PIN, 1);

    SSYNC();

 

    bfin_write_TIMER_ENABLE(1 << TIMER_BACKLIGHT);

    SSYNC();

 

    local_irq_restore(flags);

}

 

I make another  test with this parameters

 

PPICLK = 125 MHZ / 40 = 3125000 Hz (Period of 320 ns)

 

The result is the same, the TMR0 has a delay of 1/2 PPICLK period.

 

It seems that the TMR0 is configured by falling flag of PPICLK and the TMR1 / TMR2 are configured by rising flag.

 

There I can found the documetation of the library of TIMERS ?

 

Thanks

 

Miquel

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2010-03-17 15:23:19     Re: TFT Driver with Hardware timer

Mike Frysinger (UNITED STATES)

Message: 87343   

 

bfin_write_XXX are not "libraries".  they're writing directly to the hardware MMRs.  read the HRM for documentation.

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2010-03-18 13:09:45     Re: TFT Driver with Hardware timer

Miquel Soler i Mir (SPAIN)

Message: 87419   

 

Thanks Mike

 

I read the HRM. In pages 15-50/51/52, there are the CLK_SEL TIN_SEL ....

 

My question is : Where are in uclinux kernel the file with this options ?

 

Thanks

 

Miquel Soler i Mir

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2010-03-18 13:12:15     Re: TFT Driver with Hardware timer

Mike Frysinger (UNITED STATES)

Message: 87422   

 

just include asm/blackfin.h

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