2010-01-11 13:51:13     SMSC 91c111 driver timing issue

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2010-01-11 13:51:13     SMSC 91c111 driver timing issue

Hans Waldmann (UNITED STATES)

Message: 84419   

 

Hi PTG

 

We discovered a problem that on a few of our reference boards, we were having about 0.1 % packet loss using the smsc91c111 device and running 2008r1.

 

We found that the problem was due to that we had not connected the "ARDY" hardware signal. When that is not connected, some 370 ns delay is needed on the receive side between writing the pointer register and reading from the fifo data register.

 

We solved the problem by putting a delay loop in the macro:

 

#define _SMC_PULL_DATA(p, l)      \

do {        \

  volatile int delaycnt1=100; \

  char *__ptr = (p);     \

  int __len = (l);     \

  if ((unsigned long)__ptr & 2) {    \

   /*      \

    * We want 32bit alignment here.  \

    * Since some buses perform a full 32bit \

    * fetch even for 16bit data we can't use \

    * SMC_inw() here.  Back both source (on chip \

    * and destination) pointers of 2 bytes. \

    */      \

   __ptr -= 2;     \

   __len += 2;     \

   SMC_SET_PTR( 2|PTR_READ|PTR_RCV|PTR_AUTOINC ); \

   /* \

    * 370 ns delay needed before reading data fifo after setting \

    * ptr reg \

    */ \

   while(delaycnt1--) {}; \

  } \

  __len += 2;      \

  SMC_insl( ioaddr, DATA_REG, __ptr, __len >> 2);  \

} while (0)

 

If you have the ARDY signal connected, you probably dont need this. But we wanted to update you anyhow.

 

BR,

 

Hans

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