2009-06-30 10:02:02     Mapping FPGA SRAM onto Async Memory Bank - Corrupted Reads, doing it wrong?

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2009-06-30 10:02:02     Mapping FPGA SRAM onto Async Memory Bank - Corrupted Reads, doing it wrong?

Baird Hendrix (UNITED STATES)

Message: 76526   

 

Hello,

 

We're EE students working on a project where we need to caputre data from an FPGA and compute it using a Blackfin 537.  We have a STAMP board and the ADC-HSC-EVALC evaluation board.  Right now we're just trying to interface those two boards together and having a devil of a time.

 

The EVALC board has only connections as asynchronous memory.  I'd rather be using PPI or SPORT, but this is what we have to work with.  Right now I have a small SRAM set up in the Blackfin, and when it sees ARE and AMS3 go low it writes to the memory bus whatever is in the address called.  So far we are getting only corrupted outputs from the bank.  We are reading this in from /dev/mem, by fseek'ing to address between 0x20300000 and 0x2030FFFF.  It looks like we are only getting output between 0 and 50 decimal or so, or a -1, regardless of whether or not we read 8 bits (char) or 16 bits (short).

 

Of course we only have a few weeks to get this guy working, and the sooner the better.  Yay deadlines...

 

There doesn't seem to be a lot of information out there about interfacing the Blackfin to FPGA via the memory bus.  We only need to read addresses, not write to them.  We looked at using MTD devices for setting up communication between the two, but that seems like it would take a very long time to get a driver up and running.

 

Has anyone done this, and can anyone offer any advice?  I'm an FPGA guy myself, so the way the kernel interfaces with the blackfin memory mapping is prettymuch greek to me, but I think I'm slowly beginning to understand what is going on.  The kernel seems to place 0x20300000 in kernelspace if I understand what is going on, which is rather annoying...

 

Thanks!

 

 

 

(I'll post code later, I'm a work right now)

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2009-06-30 13:06:50     Re: Mapping FPGA SRAM onto Async Memory Bank - Corrupted Reads, doing it wrong?

Mike Frysinger (UNITED STATES)

Message: 76530   

 

all async banks should be directly addressable from userspace.  you shouldnt need to go through /dev/mem.  i dont think we've ever really tested the /dev/mem interface.  and simply setting a pointer to the async bank will probably be a lot easier to debug.

 

creating a simple MTD for the SRAM should be trivial.  look at the BF533-EZKIT and how it uses mtd-ram to create devices for the SRAM regions it has in its async banks.

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2009-06-30 13:15:29     Re: Mapping FPGA SRAM onto Async Memory Bank - Corrupted Reads, doing it wrong?

Baird Hendrix (UNITED STATES)

Message: 76534   

 

We tried doing a pointer to the async bank, but the Blackfin never even pulled the ARE or AMS3 lines low (we're trying to use async bank 3).  It would return numbers, but they would be non-sensical.

 

I'll look into how it's done on the BF533-EZKIT.  Maybe that will be fruitful.

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2009-06-30 13:19:57     Re: Mapping FPGA SRAM onto Async Memory Bank - Corrupted Reads, doing it wrong?

Mike Frysinger (UNITED STATES)

Message: 76537   

 

doing a read/write to the async bank should behave exactly the same regardless of user/supervisor mode.  the core merely puts the request out to the async bank, there is no logic there otherwise.

 

i'm pretty sure there is an EE note about hooking up a FPGA to the async bank, as well as an example FPGA add on card.

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2009-06-30 21:59:02     Re: Mapping FPGA SRAM onto Async Memory Bank - Corrupted Reads, doing it wrong?

Baird Hendrix (UNITED STATES)

Message: 76554   

 

Hey, I'm attaching two code samples.  Test2.c is the way we originally tried to interface, by pointers alone.  This method did NOT work.

 

 

 

The second is Test3.c.  This is the interface through /dev/mem we are using.

 

 

 

Any ideas where this went wrong?

 

test3.c

test2.c

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2009-06-30 22:02:47     Re: Mapping FPGA SRAM onto Async Memory Bank - Corrupted Reads, doing it wrong?

Baird Hendrix (UNITED STATES)

Message: 76555   

 

Also I'm having a hard time finding out anything about the Blackfin 533 MTD devices.  I know it exists, but looking through the code trunk I can't seem to find much.  Is the slram module the one I want to be using?

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2009-06-30 22:12:22     Re: Mapping FPGA SRAM onto Async Memory Bank - Corrupted Reads, doing it wrong?

Mike Frysinger (UNITED STATES)

Message: 76557   

 

hmm, you probably arent looking at trunk where i did the updates.  here is the snippet from trunk:

static struct platdata_mtd_ram sram_data_a = {

    .mapname   = "Flash A SRAM",

    .bankwidth = 2,

};

 

static struct resource sram_resource_a = {

    .start = 0x20240000,

    .end   = 0x2024ffff,

    .flags = IORESOURCE_MEM,

};

 

static struct platform_device sram_device_a = {

    .name          = "mtd-ram",

    .id            = 8,

    .dev = {

        .platform_data = &sram_data_a,

    },

    .num_resources = 1,

    .resource      = &sram_resource_a,

};

 

then use the MTD_PLATRAM driver

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2009-07-01 09:07:50     Re: Mapping FPGA SRAM onto Async Memory Bank - Corrupted Reads, doing it wrong?

Baird Hendrix (UNITED STATES)

Message: 76593   

 

We're going to give that a shot tonight.  I'll post back to let you know how it goes.

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2009-07-09 14:49:18     Re: Mapping FPGA SRAM onto Async Memory Bank - Corrupted Reads, doing it wrong?

Theo Verelst (NETHERLANDS)

Message: 76978   

 

Hi, you might want to look at my example:

 

   www.theover.org/Synth

 

The BF533 simply accesses the CPLD mapped into its memory space.

 

Theo Verelst

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