2009-03-19 16:09:25     GPIO assisted FLASH access and memory mapped FPGA

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2009-03-19 16:09:25     GPIO assisted FLASH access and memory mapped FPGA

Ashish Gupta (INDIA)

Message: 71276   


We're currently at the final stages of hardware design for a Blackfin BF527 based board which has 64MB SDRAM, 16MB NOR FLASH, an FPGA (which needs to be mapped to the EBIU AMC interface) and some other peripherals.


- 16 MB NOR FLASH Addressable by 8 banks, 2MB each (AMS0, AMS1 connected), we've added 3 GPIO lines for "GPIO assisted FLASH" addressing to go to upper access full 16MB FLASH


- We need to build memory mapped interface to the FPGA, for which we plan to use the EBIU's AMC and hence have reserved the upper two AMS lines AMS2 and AMS3 for it, we'll design the digital interface block inside the FPGA so that it can work with the Blackfin AMC, as far as the Blackfin is concerned, it will think it talking to another memory device


We need to confirm whether our following approach is A) Technically correct B) Architechturally sound, so that others in the community can benefit. Also please point to any links if someone has interfaced Blackfin to an FPGA using the memory map scheme.






We referred to the following page on the documentation wiki: http://docs.blackfin.uclinux.org/doku.php?id=linux-kernel:mtd, and understand that the mapper file "linux-2.6.x/drivers/mtd/maps/gpio-addr-flash.c" written by Mike is the way to implement this functionality. Also that GPIO's information should be advertised in the platform file "linux-2.6.x/arch/blackfin/mach-bf527/boards/"


Following is a code snippet that we plan to add to the board specific file "linux-2.6.x/arch/blackfin/mach-bf527/boards/ourboard.c"



static unsigned custom_flash_gpios[]={GPIO_PH13, GPIO_PH12, GPIO_PH11};


static struct resource custom_flash_resource[] = {


                .name  = "cfi_probe",

                .start = 0x20000000,

                .end   = 0x201FFFFF,

                .flags = IORESOURCE_MEM,

        }, {

                .start = (unsigned long)custom_flash_gpios,

                .end   = ARRAY_SIZE(custom_flash_gpios),

                .flags = IORESOURCE_IRQ,




static struct platform_device custom_flash_device = {

        .name          = "gpio-addr-flash",

        .id            = 0,

        .dev = {

                .platform_data = &custom_flash_data,


        .num_resources = ARRAY_SIZE(custom_flash_resource),

        .resource      = custom_flash_resource,






Some specific questions: -


Q1. What other things need to be done apart from editing the platform file as above and including the including "GPIO-assisted Flash Chip Support" in the uclinux build?


Q2. Will the same scheme work for the FPGA memory bank and the same FLASH driver, or we have to write our own driver to access FPGA? I understand that FLASH drivers use a chip driver for accessing a specific FLASH chip family, in our case however we don't need to issue any specific read/write commands, the digital block in the FPGA will be so designed that it will putout the appropriate data on the bus as soon as the adress is assued and the AMC control lines asserted.


Q3. How the application or file system can access the FPGA?


Its better we understand these issues now before locking down the harware design


Thanks and regards






2009-03-19 17:43:01     Re: GPIO assisted FLASH access and memory mapped FPGA

Mike Frysinger (UNITED STATES)

Message: 71281   


you need to actually link the platform resources into the platform_device array


i guess you could write your own "chip driver" for the fpga that doesnt actually do anything, but i'm only guessing here.  otherwise you'd have to write your own driver.  as for how you'd interact with that driver, that is completely up to you.




2009-03-19 22:16:51     Re: GPIO assisted FLASH access and memory mapped FPGA

Ashish Gupta (INDIA)

Message: 71287   




but the general approach of reserving AMS0,AMS1 for the 16MB FLASH and augmenting with 3 GPIOs + reserving AMS3, AMS4 for FPGA seems sound to you?


the other way way we can do it is bring all 4 AMS lines to both FLASH and FPGA and augment FLASH with 2 GPIOs + FPGA gets its own GPIO for CS.


Which approach do you think is better software wise?








2009-03-20 00:03:31     Re: GPIO assisted FLASH access and memory mapped FPGA

Mike Frysinger (UNITED STATES)

Message: 71289   


the kernel doesnt really care what flash bank mappings, just that the address range is contigious.  so the way you have ASM0/ASM1 for the flash with GPIOs to select the higher lines should work fine.  using more/less GPIOs wouldnt really affect performance ... once you move from pure ASM address lines to augmenting with GPIOs, performance will be about the same regardless of how many GPIOs are used to assist.