2009-02-18 06:11:26     core B start/stop using SICA_SYSCR bit 5

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2009-02-18 06:11:26     core B start/stop using SICA_SYSCR bit 5

Enrik Berkhan (GERMANY)

Message: 69553   

 

Hi,

 

in the Wiki (https://docs.blackfin.uclinux.org/doku.php?id=core_b) it's stated that core B of BF561 can be started and stopped using SICA_SYSCR bit 5.

 

AFAICS, that is wrong. You can only unlock core B once after hard reset. Further writes to SICA_SYSCR bit 5 have no effect. So some inter-core comm is needed to stop and re-start core B is necessary once it has been unlocked.

 

Or am I possibly doing something wrong? What I do is:

 

    load core B

    start core B

    echo 0x20 > "/sys/kernel/debug/blackfin/SICA Register File/SICA_SYSCR"

    core B still running

 

(I had started a thread here for discussion of a reliable way to stop and re-start core B without reboot in the end of 2007, IIRC. Just wanted to re-check that writes to SICA_SYSCR bit 5 still have no effect but the first one.)

 

Enrik

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2009-02-18 13:38:42     Re: core B start/stop using SICA_SYSCR bit 5

Mike Frysinger (UNITED STATES)

Message: 69580   

 

that page talks about a framework that uses the SYSCR registers for communication.  it doesnt mean that the register can be used to actually start/stop the core in hardware.

 

there is no way to stop core b once it has started.

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2009-02-18 22:07:29     Re: core B start/stop using SICA_SYSCR bit 5

Sonic Zhang (CHINA)

Message: 69592   

 

It is better to call it "PAUSE" or "HALT" instead of "STOP" in that document. Core B can be halted by bit 5 in register SICA_SYSCR. But, if you enable this bit again, CORE B resumes from where it halts. So, IPI is still necessary when RUN is called.

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