2005-11-28 16:24:52     SCLK speed on STAMP

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2005-11-28 16:24:52     SCLK speed on STAMP


Message: 4324    Hi,


What is the maximum SCLK speed I should be able to run on a BF533 STAMP board (rev 1.1).


Basically I currently have SCLK set to 124MHz ( multipler 45, divider 4). I am acquiring data via the PPI port, using an external 60MHz PPI_CLK, but very occationally finding some strange glitches in the data.


Is it necessary to set SCLK to a low frequency? Elsewhere in the forum I have seen mention of 99MHz ( multiplier 45, divider 5 ) or 80MHz ( multiplier 36, divider 5 ). Clearly I would need to modifiy the frequency of the external PPI_CLK.








2005-11-28 20:10:25     RE: SCLK speed on STAMP

Martijn van Eeten (NETHERLANDS)

Message: 4325    According to http://blackfin.uclinux.org/frs/download.php/458/readme.txt

revision 1.1 has been tested at 80 MHz - no higher. You can upgrade

your STAMP to version 1.2 using the instructions from


which is supposed to cope with a 110 MHz bus.




2005-11-29 07:58:26     RE: SCLK speed on STAMP

Michele d'Amico (ITALY)

Message: 4327    Take a look this thread http://blackfin.uclinux.org/forum/message.php?msg_id=4325








2005-11-29 08:02:29     RE: SCLK speed on STAMP

Michele d'Amico (ITALY)

Message: 4328    I'm sorry: wrong cut&paste. The right link is









2005-11-29 09:16:37     RE: SCLK speed on STAMP

Alexander Antonenko (UKRAINE)

Message: 4330    I have the same problem.

But my board rel.1.1 do not work on uClinux-distR3

I try 389Mhz/79Mhz and 389Mhz/66Mhz

In link change only SPORT, can I rework SDRAM to rel.1.2 ?




2005-11-29 17:37:19     RE: SCLK speed on STAMP


Message: 4333    The re-work has nothing to do with the SCLK speed issue - it only resolves a SPORT channel switch issue.


When you say that R3 doesn't work - What problem are you having?







2005-11-29 20:56:51     RE: SCLK speed on STAMP

Martijn van Eeten (NETHERLANDS)

Message: 4337    Robin,


Do you mean that applying the version 1.2 modifications to a version 1.1 board will _not_ make it run reliably at a 100 MHz SCLK instead of 80 MHz?

In other words, there are other differences?


Or should a v1.1 board be just as stable at 100 MHz as a v1.2 board but has just not been tested at that speed?




2005-11-30 00:14:06     RE: SCLK speed on STAMP


Message: 4338    Martijn:


The short answer - is yes - no amount of modifications will make a 1.1 board work faster (that I have found).


The long answer history on the project was:


When we were developing the kernel - we wanted to make a low cost board - that means 4 layers. The folks who make EZ-kits (which are sometimes 12+ layers, laughed saying it couldn't be done without major problems).


We made a 0.8 board (10) - 4 layers - they worked great. We ran them fast (we had 750MHz parts of the first few), and ran them as fast as possible.


We made 150 of a 0.9 board (basically the same as the 0.8 board) - This time with 600MHz on them - they also worked fine. We did release testing in an oven - up to +40 and down to -40 : Everything was fine - it worked at speed. Most of these went to developers, and early adopters.


We made 1000 of the 1.0 and 1.1 boards with 500MHz parts on them. We tested the first bunch off the batch, and they worked great. The test process for these boards - was boot them into uCinux and run some software. At this time - we were running U-Boot and the kernel at 80MHz.


When we made the 1.2 boards (another 500+), we made some changes on the SPORTS to fix an issue we saw on some 1.1 boards (this is what the re-work fixes), and in order to increase robustness, changed some of the SDRAM clocking routing, and added termination to SCLK. We noticed that the SCLK change made things wonky at high speeds, and low temperatures. We fixed it the best we could, but putting the best termination resistors on the SCLK, and during testing of these boards - we run an non-uClinux application which tests all combinations of SCLK under 110MHz.


We then went back, and saw some of the same on the 1.1 boards. Since they were only tested at 80MHz - that is the only thing I can say. They are tested at 80MHz. Some will run at 140MHz+, some won't. Some will fail at 100MHz (pretty rare).


But I don't know which board you have - so for a 1.1 board - all I can say is don't run them over 80MHz. Where will it fail, is a combination of temperature, and the lot code of SDRAMs that you have.


The problem was root caused to having the 4 SDRAM devices - 128 Meg in a 4x configuration. There were no series termination on the databus for the SDRAMs - they should have been there.


The moral of the story is that when people laugh at you - do more simulation, and testing one lot code of SDRAMs don't count.


For the 537-STAMP - we borrowed the EZ-kit design - it runs at speed (past 133MHz), but is currently 8 layers, and has 64Meg (in a x8 config) - it seems to be working well. (but it is more $, becuase of the extra 4 layers).


I'm not sure if that helps or not.






2005-11-30 07:51:32     RE: SCLK speed on STAMP

Alexander Antonenko (UKRAINE)

Message: 4343    Last version that work on my board Rel.1.1 - CVC from 15.03.2005.

I download new version in september it do not work. And last version the same. I try change freq.

and switch off DCACHE but this do not help me.




2008-12-18 01:31:38     RE: SCLK speed on STAMP

roopesh motewar (INDIA)

Message: 66825   


hi all


          what is maximum bit rate of the sport ? how to use.


hi want to transfer the serial data over ethrnet in the range of mbps is it posssible using sport


if yes ? how








2008-12-18 10:09:10     RE: SCLK speed on STAMP


Message: 66864   




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