2008-11-07 18:53:58     uimage display garbage for bf527 custom board

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2008-11-07 18:53:58     uimage display garbage for bf527 custom board

Dominic On (CANADA)

Message: 64866   

 

Please help!

 

When loading uimage, then dispaly garbage, and I try to change the baud rate to different speed at the Hyper Terminal when boot, but nothing is display in readable text. Look like uimage has the communcation config settings different than 57600, 8-N-1-None.  Here is the display shown below:

 

U-Boot 1.1.6-svn1422 (ADI-2008R1.5) (Nov  7 2008 - 15:48:08)

 

CPU:   ADSP bf527-0.0 (Detected Rev: 0.0)

Board: Dominic's BF527 board

       Support: http://blackfin.uclinux.org/

Clock: VCO: 400 MHz, Core: 400 MHz, System: 133 MHz

RAM:   32 MB

Flash:  2 MB

In:    serial

Out:   serial

Err:   serial

Net:   Blackfin EMAC

MAC:   96:9D:75:34:05:01

Hit any key to stop autoboot:  5  4  3  2  1  0

 

EEPROM @0x0 read: addr 01000000  off 31000  count 3866624 ... done

## Booting image at 01000000 ...

   Image Name:   Linux-2.6.22.19-ADI-2008R1.5-svn

   Created:      2008-11-07  22:43:42 UTC

   Image Type:   Blackfin Linux Kernel Image (gzip compressed)

   Data Size:    3816600 Bytes =  3.6 MB

   Load Address: 00001000

   Entry Point:  001a4000

   Verifying Checksum ... OK

   Uncompressing Kernel Image ... OK

Starting Kernel at = 1a4000

 

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and more garbage text, I just copied partial of the display.....

 

=================================================================================

 

I also just update the uclinux-dist for "2008R1.5" from SVN

 

The board has 2M paralell flash, 8M SPI Flash, 32M RAM

 

Uses UART0, Baud=57600, 8-N-1-None.

 

uimage config using menuconfig and add UART0 with DMA, keep UART1.  (but if I remove UART1, there is no different, the problem is still there)

 

The u-boot is boot from SPI Flash.

 

U-BOOT address is from 0 to 0x2FFFF

 

Environment address is from 0x30000 to 0x31000

 

UIMAGE address is from 0x31000 to 0x3FFFFF

 

Here is the enviroment:

 

bfin> printenv

bootargs=root=/dev/mtdblock0 rw earlyprintk=serial,uart0,57600 console=ttyBF0,57600

bootcmd=run ramargs;run addip;run add_eth_args;run spiflashboot

bootdelay=5

baudrate=57600

loads_echo=1

ipaddr=192.168.0.15

serverip=192.168.0.2

rootpath=/romfs

gatewayip=192.168.0.1

netmask=255.255.255.0

hostname=bf527-Dominic

loadaddr=0x1000000

ubootfile=u-boot.ldr

update=tftp $(loadaddr) $(ubootfile);eeprom write $(loadaddr) 0x0 $(filesize)

addip=set bootargs $(bootargs) ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname):eth0:off

ramargs=set bootargs root=/dev/mtdblock0 rw earlyprintk=serial,uart0,57600 console=ttyBF0,57600

ramboot=tftp $(loadaddr) uImage;run ramargs;run addip;bootm

nfsargs=set bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath),tcp,nfsvers=3

nfsboot=tftp $(loadaddr) vmImage;run nfsargs;run addip;bootm

flashboot=bootm 0x20100000

imgaddr=0x31000

imgsize=3b0000

spiflashboot=eeprom read $(loadaddr) $(imgaddr) $(imgsize);bootm

eth_a_host=00:01:9c:01:23:45

eth_a_gadget=00:01:9c:67:89:ac

eth_args=g_ether.host_addr=$(eth_a_host)

eth_args=$(eth_args) g_ether.dev_addr=$(eth_a_gadget)

add_eth_args=set bootargs $(bootargs) $(eth_args)

ethaddr=96:9D:75:34:05:01

stdin=serial

stdout=serial

stderr=serial

ethact=Blackfin EMAC

 

Environment size: 1248/4092 bytes

bfin>

 

 

 

Regards,

 

Dominic

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2008-11-08 06:33:52     Re: uimage display garbage for bf527 custom board

Mike Frysinger (UNITED STATES)

Message: 64886   

 

you can try this page and see if you get any useful info out of the kernel:

http://docs.blackfin.uclinux.org/doku.php?id=linux-kernel:debug:post_mortem

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2008-11-10 12:58:19     Re: uimage display garbage for bf527 custom board

Dominic On (CANADA)

Message: 64962   

 

Thank you Mike,

 

I found the problem,  the clock setting for eval board BF527-Ezkit is 25MHz, and my board is 20MHz., so I change it by using memnuconfig:

Blackfin Processor Options --> Board Customizations --> Frequency of the crystal on the board in Hz --> 20000000.

 

 

 

Regards,

 

Dom

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2008-11-11 04:16:23     Re: uimage display garbage for bf527 custom board

Michael McTernan (UNITED KINGDOM)

Message: 65000   

 

Also note that you may also wish to increase the VCO multiplier so the Blackfin clock remains the same/similar despite the board clock being slower.  e.g. if the VCO multiplier was 24 @ 25MHz board clock, the core clock would be 600MHz, so @ 20MHz the VCO multiplier would need to be 30 to achieve the same core speed.

 

These settings are also under Board Customizations:

 

  │ │(24)    VCO Multiplier                                             

  │ │      Core Clock Divider (1)  --->                                 

  │ │(5)   System Clock Divider

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2008-11-11 15:39:28     Re: uimage display garbage for bf527 custom board

Dominic On (CANADA)

Message: 65056   

 

Thanks Michael,

 

My board Crystal clock is 20Mhz, and the core clock is 400 MHz, and System Clock is 133 Mhz, so, I already set the CONFIG_VCO_MULT=20, CONFIG_CCLK_DIV=1, and CONFIG_SCLK_DIV=4.

 

BTW, I could not make the USB controller to work, is it because of the clock rate different?  It works on the Eval board, but not in my board.

 

USB PLL OSC Control Register

 

The USB controller requires an internal clock of 960 MHz.  my board has 20 MHz clock

 

USB PLL output frequency = (2 x USB_MSEL x CLKIN_FREQ) / (USB_DF + 1)

 

Use USB_MSEL = 24 and USB_DF = 0.

 

 

 

Where can I set the USB_MSEL and USB_DF ?  I search thru the source code, but could not find anything about this info!, but found CONFIG_USB_CLOCK=0x0001BBBB

 

 

 

Please help.

 

Regards,

 

Dom

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2008-11-11 16:48:41     Re: uimage display garbage for bf527 custom board

Dominic On (CANADA)

Message: 65061   

 

OK, I found where the USB_MSEL and USB_DF should be changed, but this value is hard-coded as 0x30A8 in file:

 

/uclinux-dist/linux-2.6.x/drivers/usb/msub/blackfin.c, line 392. ==> bfin_write_USB_PLLOSC_CTRL(0x30A8).

 

The value (0x30A8) in function call above should be settable from the menuconfig to have the settings for PLL_STABLE, FORCE_MSEL, USB_MSEL and USB_DF.

 

The register USB_PLLOSC_CTRL describes in document ADSP-BF52x Blackfin Processor Hardware Reference (Vol. 2), Rev. 0.3, September 2007, page 638-639.

 

So for my board, the PLL_STABLE=0, FORCE_MSEL=1, USB_MSEL=0x18, USB_DF=0.  So I change the hardcoded value from 0x30A8 to 0x30B0.

 

 

 

Regards,

 

Dom

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