2008-08-28 07:22:46     Erroneous Write Access on L2 SRAM

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2008-08-28 07:22:46     Erroneous Write Access on L2 SRAM

Stephen Sheldon (GERMANY)

Message: 61251   

 

Hi,

 

I use the BF561 EZ-Lite with uClinux 2008R1-RC8.

 

I wrote an application for core A and an application for core B. They communicate via L2 SRAM.

 

Unfortunately the applications don't run stable. After a long search I found the error. :-)

 

The write access on L2 SRAM works erreneous. When I write some data into L2, sometimes the value at the specific adress doesn't match with the value I wrote into. To write and read data in L2 I use direct pointers.

 

I attached a little test application which shows the wrongdoing. With the two #defines you can switch between a read only test and a read/write test. The read test should pass. The read/write test should have a output like this:

 

OK *fpTestfkt(0x  A7161C) == testfkt(0x  A7161C)

OK *ppPtr(0x    ADDE) == pPtr(0x    ADDE)

OK *pCounter(0x 1000002) == counter(0x 1000002)

OK *pData(0x    ABCD) == data(0x    ABCD)

OK *fpTestfkt(0x  A7161C) == testfkt(0x  A7161C)

OK *ppPtr(0x    ADDE) == pPtr(0x    ADDE)

OK *pCounter(0x 2000002) == counter(0x 2000002)

OK *pData(0x    ABCD) == data(0x    ABCD)

OK *fpTestfkt(0x  A7161C) == testfkt(0x  A7161C)

OK *ppPtr(0x    ADDE) == pPtr(0x    ADDE)

OK *pCounter(0x 3000002) == counter(0x 3000002)

OK *pData(0x    ABCD) == data(0x    ABCD)

OK *fpTestfkt(0x  A7161C) == testfkt(0x  A7161C)

OK *ppPtr(0x    ADDE) == pPtr(0x    ADDE)

OK *pCounter(0x 4000002) == counter(0x 4000002)

OK *pData(0x    ABCD) == data(0x    ABCD)

OK *fpTestfkt(0x  A7161C) == testfkt(0x  A7161C)

OK *ppPtr(0x    ADDE) == pPtr(0x    ADDE)

OK *pCounter(0x 5000002) == counter(0x 5000002)

OK *pData(0x    ABCD) == data(0x    ABCD)

OK *fpTestfkt(0x  A7161C) == testfkt(0x  A7161C)

OK *ppPtr(0x    ADDE) == pPtr(0x    ADDE)

OK *pCounter(0x 6000002) == counter(0x 6000002)

OK *pData(0x    ABCD) == data(0x    ABCD)

 

 

ERROR *fpTestfkt(0x       0) != testfkt(0x  A7161C)

ERROR *ppPtr(0xCA66010A) != pPtr(0x    ADDE)

ERROR *pCounter(0x 6B26546) != counter(0x 6B26546)

ERROR *pData(0x    ABCD) != data(0x    ABCD)

 

 

OK *fpTestfkt(0x  A7161C) == testfkt(0x  A7161C)

OK *ppPtr(0x    ADDE) == pPtr(0x    ADDE)

OK *pCounter(0x 7000002) == counter(0x 7000002)

OK *pData(0x    ABCD) == data(0x    ABCD)

 

 

ERROR *fpTestfkt(0x       E) != testfkt(0x  A7161C)

ERROR *ppPtr(0x       6) != pPtr(0x    ADDE)

ERROR *pCounter(0x 7FFDD52) != counter(0x 7FFDD52)

ERROR *pData(0x    ABCD) != data(0x    ABCD)

 

 

OK *fpTestfkt(0x  A7161C) == testfkt(0x  A7161C)

OK *ppPtr(0x    ADDE) == pPtr(0x    ADDE)

OK *pCounter(0x 8000002) == counter(0x 8000002)

OK *pData(0x    ABCD) == data(0x    ABCD)

 

 

ERROR *fpTestfkt(0x       0) != testfkt(0x  A7161C)

ERROR *ppPtr(0x       0) != pPtr(0x    ADDE)

ERROR *pCounter(0x 82BCF96) != counter(0x 82BCF96)

ERROR *pData(0x    ABCD) != data(0x    ABCD)

 

.....

 

 

 

(If you don't understand the code, pls ask. The comments are in german Sorry. But its a very simple test application)

 

 

 

Does someone have this problem too? Or is my hardware broken?

 

 

 

Best regards

 

Stephen

 

 

 

 

 

 

 

L2_Access-Test.cpp

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2008-08-28 13:37:21     Re: Erroneous Write Access on L2 SRAM

Stephen Sheldon (GERMANY)

Message: 61272   

 

When I disable DCACHE in the uClinux menuconfig, it works.

 

But i have set all L2 variables volatile. So they shouldn't been cached.

 

Also I thought the default config of uClinux dosn't cache any L2 memory areas.

 

 

 

Someone can help me please?

 

 

 

Regars

 

Steph

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2008-08-28 21:41:45     Re: Erroneous Write Access on L2 SRAM

Robin Getz (UNITED STATES)

Message: 61290   

 

Stephen:

 

Sorry for delay - we have been a little swamped the past few days...

 

I will have a look tomorrow.

 

 

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2008-08-28 23:53:34     Re: Erroneous Write Access on L2 SRAM

Yi Li (CHINA)

Message: 61301   

 

Please check your CPLB setting via /proc/cplbinfo. Here is mine:

 

Data CPLB entry:                                                              

Address         Data    Size    Valid   Locked  Swapin  iCount  oCount        

0x00000000      0x00083 1K      Y       Y        0      0       0             

0xff800000      0x3009f 4M      Y       Y        1      0       0             

0x00000000      0x3d09f 4M      Y       Y        2      0       0             

0x00400000      0x3d09f 4M      Y       Y        3      0       0             

0x00800000      0x3d09d 4M      Y       N       -1      0       1             

0x00c00000      0x3d09d 4M      Y       N       -1      0       1             

0x01000000      0x3d09d 4M      Y       N       -1      0       1             

[snip]        

0xfeb00000      0x2009d 1M      Y       N       -1      0       0             

0xef000000      0x2d09d 1M      Y       N       -1      0       0             

 

As we can see, the L2 (0xfeb00000) is configured as non-cacheable on my system. And I run your test code, it works well without error.

 

And "volatile" cannot prevent a variable being cached.

 

-Yi

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2008-08-29 05:35:30     Re: Erroneous Write Access on L2 SRAM

Stephen Sheldon (GERMANY)

Message: 61371   

 

my looks like this.

 

I tried it with write_trough and write_back cache policy. The 0xfeb00000 entry is the same.

 

Data CPLB entry:

Address         Data    Size    Valid   Locked  Swapin  iCount  oCount

0x00000000      0x00083 1K      Y       Y        0      0       0

0xff800000      0x3009f 4M      Y       Y        1      0       0

0x00000000      0x3109f 4M      Y       Y        2      0       0

0x00400000      0x3109f 4M      Y       Y        3      0       0

0x00800000      0x3109f 4M      Y       Y        4      0       0

0x00c00000      0x3109f 4M      Y       Y        5      0       0

0x01000000      0x3109d 4M      Y       N       -1      0       1

|snip]

0x2f400000      0x3009d 4M      Y       N       -1      0       0

0x2f800000      0x3009d 4M      Y       N       -1      0       0

0x2fc00000      0x3009d 4M      Y       N       -1      0       0

0xfeb00000      0x2009d 1M      Y       N       13      1       0

0xef000000      0x2109d 1M      Y       N       -1      0       0

 

 

What is Swapin and iCount means?

 

 

 

Robin: No problem. I am glad that you help me at all. :-)

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2008-08-29 07:08:19     Re: Erroneous Write Access on L2 SRAM

Yi Li (CHINA)

Message: 61372   

 

This looks unreasonable to me. Your L2 is also set as non-cacheable.

 

The name is kind of missleading. "Swapin=13" means this entry is in the 13rd entry of CPLB table, i.e, '-1' means this entry is not in CPLB table. "iCount=1" mean it has been swap in once.

 

-Yi

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2008-08-29 07:28:55     Re: Erroneous Write Access on L2 SRAM

Stephen Sheldon (GERMANY)

Message: 61373   

 

So the difference betweens your uClinux version and my is that your 0xFEB00000 entry is not in the CPLB table. Where can I kick this entry out of my CPLB table? :-)

 

Do you agree that the reason of the wrongdoing has something to do with the DCACHE?

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2008-08-30 01:20:11     Re: Erroneous Write Access on L2 SRAM

Mike Frysinger (UNITED STATES)

Message: 61395   

 

the 0xfeb00000 entry should be the same regardless of your cache settings.  if you actually decode the field (read the Blackfin PRM), you'll see that it declares the region as uncached exactly like it should be doing.

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2008-08-30 01:21:21     Re: Erroneous Write Access on L2 SRAM

Mike Frysinger (UNITED STATES)

Message: 61396   

 

how exactly are you compiling the code ?  what kernel/toolchain version ?  when asking questions, please describe your setup.

 

i did notice your usage of volatile is wrong in at least one place (ppPtr) ...

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2008-09-01 06:33:26     Re: Erroneous Write Access on L2 SRAM

Stephen Sheldon (GERMANY)

Message: 61471   

 

Linux version:  2.6.22.18-ADI-2008R1-svn

Default configuration. I have just turned of watchdog.

 

3 blackfin toolchain packages are installed on my Desktop PC :

- blackfin-toolchain version:  08r1-8

- blackfin-toolchain-elf-gcc-4.1 version: 08r1-8

- blackfin-toolchain-uclibc-full  version: 08r1-8

 

U-Boot 1.1.6-svn1112

 

 

 

I compile the code with no specific flags. No optimize flags.

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2008-09-01 08:26:05     Re: Erroneous Write Access on L2 SRAM

Stephen Sheldon (GERMANY)

Message: 61476   

 

I have just noticed that my cache wasn't configurate as writethrough. don't no why. I though writethrough is default.

With writetrough cache the test application works fine.

 

But why is there a difference between this two cache configurations, when L2 SRAM isn't configurate as cacheable?

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2008-09-01 08:52:39     Re: Erroneous Write Access on L2 SRAM

Stephen Sheldon (GERMANY)

Message: 61479   

 

would you like to tell me what's wrong with my usage of volatile? :-)

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2008-09-01 12:03:02     Re: Erroneous Write Access on L2 SRAM

Mike Frysinger (UNITED STATES)

Message: 61488   

 

"volatile void **ptr" declares the pointers as volatile, not the stuff they're pointing to.  so gcc will make sure to reload the array of pointers everytime, but not the things that array of pointers points to.

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2008-09-03 03:31:43     Re: Erroneous Write Access on L2 SRAM

Stephen Sheldon (GERMANY)

Message: 61558   

 

Ok, this is wanted like this. :-)

 

But why do I have to configurate the cache as writethrough. In my opinion, this shouldn't has any effect to the L2 access, because it isn't set as cacheable. I think L2 is set as non cacheable. I do not set anywhere any cache settings exepting writeback/writethorugh in the kernel "menu config".

 

Where do i change more cache settings?

 

Do you get some errors if you set cache as writeback?

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