2008-08-27 05:37:48 BF548 SCLK
Patrick Mc Donnell (IRELAND)
If I set my VCO_MULT to 21 and SCLK_DIV to 4 and CCLK_DIV to 1 in my u-boot settings (ie edit u-boot/include/configs/bf548-ezkit.h) with my clock being 25MHz, am i right in thinking that my SCLK will now equal 131.25MHz?
Also if I set my VCO_MULT to 20 and SCLK_DIV to 4 and CCLK_DIV to 1 in my kernel settings
Blackfin Processor Options --->
Clock Settings --->
[*] Re-program Clocks while Kernel boots?
(20) VCO Multiplier
(1) Core Clock Divider (NEW)
(4) System Clock Divider (NEW)
[ ] Half ClockIn
[ ] Bypass PLL
with my clock being 25MHz, am i right in thinking that my SCLK will now equal 125MHz?
Lastly, if i have both these settings which SCLK will my board use, the u-boot one or my kernel one?
2008-08-27 16:12:29 Re: BF548 SCLK
Mike Frysinger (UNITED STATES)
the clock algorithms are described in the HRM/PRM in many places. the u-boot code as well describes it:
Core: (CLKIN / (2 ^ CLKIN_HALF) * VCO_MULT) / CCLK_DIV
System: (CLKIN / (2 ^ CLKIN_HALF) * VCO_MULT) / SCLK_DIV