2008-08-19 13:50:19     SDRAM timings

Document created by Aaronwu Employee on Aug 7, 2013
Version 1Show Document
  • View in full screen mode

2008-08-19 13:50:19     SDRAM timings

Michael McTernan (UNITED KINGDOM)

Message: 60663   




For the MT48LC64M4A2FB-7E part, the datasheet (rev L, 10/07) indicates in table 2 that CAS = 2 for a clock of 133MHz.  This is not setup by the kernel which always uses CAS = 3 for this part under 2008R1.5-RC3.


Similarly tRAS is spec'd at min 37ns for the 7E speed grade.  At SCLK=119402985 HZ this makes tRAS = ~4.5 = 5 cycles and at SCLK=104477612 tRAS would be 3.8 = 4 cycles.  For this speed bracket the delay is set to 6 by the kernel.


Is there any reason or bad experience for these conservative settings?








2008-08-20 01:52:04     Re: SDRAM timings

Frank Van Hooft (CANADA)

Message: 60709   


This maybe partially answers your question:




"layout compromises" ?




2008-08-20 04:44:01     Re: SDRAM timings

Michael McTernan (UNITED KINGDOM)

Message: 60741   


From that link:


"To accommodate the maximum number of configuration options, some layout compromises were made. Version 1.2 STAMP board SDRAM is being tested at 110 MHz. Setting the SDRAM frequency higher than 110 MHz may cause any number of errors"


That maybe it, but I'd have though that this just restricts SCLK to no more than 110MHz on a STAMP, rather than put the specific SDRAM timings into undefined boxes on the datasheet (the -7E part only has an access time specified at CAS=2 for 133MHz with CAS=3 at that same speed having no definition).


I'm not using a STAMP in anycase, so I think I'll go with CAS=2 and fix up the timings so that they are within the matrices on the datasheet and test in from there.