2008-06-14 11:51:00     Making async banks non-cacheable?

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2008-06-14 11:51:00     Making async banks non-cacheable?

Steve M (UNITED STATES)

Message: 57303   

 

Hello

 

I've got a BF537 (actually a Bluetechnix module) running uClinux on a custom board where a bunch of I/O registers are mapped into the async memory bank 2. I don't have the technical understanding to write a full kernel driver, so I am accessing these registers directly from userspace (with memory protection turned off). However, to make this work, I must disable the dcache, so that I can read fresh values of those registers every time.

 

I still would like to use the dcache, however, for the remaining memory space. Is there an easy way to make certain addresses, or the entire async memory space, non-cacheable?

 

Thanks

 

Steve

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2008-06-14 14:33:09     Re: Making async banks non-cacheable?

Robin Getz (UNITED STATES)

Message: 57306   

 

Steve:

 

I thought by default the async was all non-cacheable.

 

Have a look in /proc/cplbinfo

 

-Robin

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