2008-04-28 10:29:59     MT48LC8M16A2TG SDRAM chip configure

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2008-04-28 10:29:59     MT48LC8M16A2TG SDRAM chip configure

vijaya joseph (INDIA)

Message: 55138   

 

Hi

 

I am using BF561 based hardware with a SDRAM chip MT48LC8M16A2TG.

 

How can I select this chip drivers in UClinux kernel using make menuconfig?

 

Actually we are using two of these chips in parallel.So our hardware has 32 Mbytes.

 

I am using 2007 R1 version.

 

Best regards,

 

Vijaya

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2008-04-28 11:15:40     Re: MT48LC8M16A2TG SDRAM chip configure

Mike Frysinger (UNITED STATES)

Message: 55150    if you dont reprogram the clocks, there's no need to explicitly specify the memory chip for linux

 

program the clocks with u-boot

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2008-04-29 04:46:36     Re: MT48LC8M16A2TG SDRAM chip configure

vijaya joseph (INDIA)

Message: 55207   

 

Hi,

 

I disable clock settings and compiled . Using that UImage I am getting the following error.

 

code=[0x21], stack frame=0x1f9b9f0, bad PC=0x1fc0130

 

Am I missing something?

 

Is this error related to cache? Where is the definitions for the error code? Code=0x21 means which error?

 

I don't use some portion of the SDRAM as cache.

 

How to edit cplb table entires?

 

Best regards,

 

Vijaya

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2008-04-29 19:05:39     Re: MT48LC8M16A2TG SDRAM chip configure

Mike Frysinger (UNITED STATES)

Message: 55255    upgrade your u-boot to 2008R1 and you'll get a much better trace back.  you also wont have to mess with CPLB tables at all.

 

i dont know what you mean by "I don't use some portion of the SDRAM as cache."  all of SDRAM gets cached, end of story.

 

as for what 0x21 means, look it up in the Blackfin PRM.

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