2008-03-26 05:24:25     Working of Sport

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2008-03-26 05:24:25     Working of Sport

a manjula (INDIA)

Message: 53042    Hi,

 

     I am configuring sport to get TCLK=RCLK=256khz and TFS=RFS=16Khz.

My CCLKIN=24.576Mhz, VCO=CCLKIN*20, CCLK=VCO, SCLK=VC0/5.

I am getting SCLK=98.3Mhz on my scope, but I am not getting TCLK/RCLK./RFS/TFS

on scope.  When I executed my sport test program, I am getting exact values of all clocks.

Can anybody tell me why I am not getting TCLK/RCLK./RFS/TFS clocks on scope and I

came to know that it is not possible to get sport clock through internal crystal.  Is it true.

I have attached my configuration file as an attachment.  Can anybody guide me if I am wrong.

Sorry, I am not able to attach my configuration file, therefore I am giving the details below

 

/* PLL_CTL Masks                                                                    */

#define DF              0x0000  /* 0: PLL = CLKIN, 1: PLL = CLKIN/2             */

#define PLL_OFF         0x0000  /* PLL  Powered                                 */

#define STOPCK          0x0000  /* Core Clock On                                */

#define PDWN            0x0000  /* All Internal Clocks on                       */

#define IN_DELAY        0x0000  /* Do not add Input Delay                       */

#define OUT_DELAY       0x0000  /* Do not add Output Delay                      */

#define BYPASS          0x0000  /* Do not Bypass the PLL                        */

#define MSEL            0x2800  /* Multiplier Select For CLKIN/VCO Factors(Multiplier factor is 20)      */

#define SSEL            0x0005 /* System Select SCLK=VCO/5                      */

#define CSEL            0x0000  /* Core Select   CCLK=VCO/1     

/* Port G Masks                                                         */

#define PG8     0x0100

#define PG9     0x0200

#define PG10    0x0400

#define PG11    0x0800

#define PG12    0x1000

#define PG13    0x2000

#define PG14    0x4000

#define PG15    0x8000

/*  *******************  PIN CONTROL REGISTER MASKS  ************************/

 

#define PGSE            0x0200  /* Port G SPORT1 Secondary Enable        */

#define PGSE_SPORT      0x0200  /*              Enable DR1SEC/DT1SEC     */

#define PGRE            0x0400  /* Port G SPORT1 Receive Enable          */

#define PGRE_SPORT      0x0400  /*              Enable DR1PRI/RFS1/RSCLK1 */

#define PGTE            0x0800  /* Port G SPORT1 Transmit Enable        */

#define PGTE_SPORT      0x0800  /*              Enable DT1PRI/TFS1/TSCLK1       */

/* *******************  SERIAL PORT MASKS  **************************************/

/* SPORTx_TCR1 Masks                                                            */

#define TSPEN       0x0001  /* Transmit Enable                                                              */

#define ITCLK       0x0002  /* Internal Transmit Clock Select                               */

#define DTYPE_NORM  0x0000  /* Data Format Normal                                                   */

#define TLSBIT      0x0010  /* Transmit Bit Order(LSB First)                                                   */

#define ITFS        0x0200  /* Internal Transmit Frame Sync Select                  */

#define TFSR        0x0400  /* Transmit Frame Sync Required Select(Require TFS for every data word)                 */

#define DITFS       0x0000  /* Data-dependent Transmit Frame Sync Select  */

#define LTFS        0x0000  /* Active High  Transmit Frame Sync Select                               */

#define LATFS       0x0000  /* Early Transmit Frame Sync Select                              */

#define TCKFE       0x0000  /* Clock Falling Edge Select(Drive data and internal FS with rising edge of TSCLK. */

 

/* SPORTx_TCR2 Masks and Macro                                                  */

#define SLEN(x)     ((x)&0x1F)  /* SPORT TX Word Length (2 - 31)                                */

#define TXSE        0x0000  /* TX Secondary Disable                                               */

#define TSFSE       0x0000  /* Normal Mode                   */

#define TRFST       0x0000  /* Left Stereo Channel first             */

 

/* SPORTx_RCR1 Masks                                                            */

#define RSPEN       0x0001  /* Receive Enable                                                               */

#define IRCLK       0x0002  /* Internal Receive Clock Select                                */

#define DTYPE_NORM  0x0000  /* Data Format Normal                                                   */

#define RLSBIT      0x0010  /* Receive Bit Order(LSB First)                                                    */

#define IRFS        0x0200  /* Internal Receive Frame Sync Select                   */

#define RFSR        0x0400  /* Receive Frame Sync Required Select                   */

#define LRFS        0x0000  /* Active High Receive Frame Sync Select                                */

#define LARFS       0x0000  /* Early Receive Frame Sync Select                               */

#define RCKFE       0x0000  /* Clock Falling Edge Select                                    */

 

/* SPORTx_RCR2 Masks                                                            */

#define SLEN(x)     ((x)&0x1F)  /* SPORT RX Word Length (2 - 31)                                */

#define RXSE        0x0000  /* RX Secondary Disable                                                  */

#define RSFSE       0x0000  /* Normal Mode                                  */

#define RRFST       0x0000  /* Left Stereo Channel first*/

 

 

 

 

 

 

Thanks in Advance.

 

Regards,

Manjula

auio_drv_sport_def.h

auio_drv_sport_def.h

auio_drv_sport_def.h

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2008-03-26 13:18:06     Re: Working of Sport

Robin Getz (UNITED STATES)

Message: 53067    Manjula:

 

I think you need to back up, and explain what you are trying to do.

 

Why not just use the existing SPORT driver?

 

-Robin

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2008-03-26 23:20:57     Re: Working of Sport

a manjula (INDIA)

Message: 53088    Hi,

 

      Thanks for the reply.  I am working on BF-537 STAMP Board.  I am using the existing sport driver

provided by uClinux only.  Here I am developing sport driver to communicate between BF-537 and Audio DSP.

Initially I want to check, whether I am getting basic clock(256khz) and frams sync(16khz) frequency.

Since BF-537 contains 25MHz clock, we have replaced 25Mhz with 24.576 Mhz, as I was not able

to generate the exact sport frequency of 256 and 16khs.   I have designed in such a way that

my

clkin=24.576Mhz,

vco=clkin * 20(24.576*20)Mhz

cclk=vco/1

sclk=vco/5.

 

     In my scope I am getting vco,cclk and sclk frequencies correctly, but I am not able to see sport frequencies on scope.

I want to know the reason for this and I want to know whether can we generate sport frequency through internal clock

correctly.

 

Regards,

Manjula

    

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2008-03-27 01:55:17     Re: Working of Sport

Yi Li (CHINA)

Message: 53095    BF537 HRM reads that:

 

"Both transmit and receive clocks can be independently generated inter-

nally or input from an external source. The ITCLK bit of the SPORTx_TCR1

configuration register and the IRCLK bit in the SPORTx_RCR1 configuration

register determines the clock source."

 

So if you set it correctly, you should be able to see the signals.

Please refer to uclinux-dist/user/blkfin-test/sport_test/sport_test.c on how SPORT is configured.

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2008-03-27 06:14:31     Re: Working of Sport

Hemanth Kumar (INDIA)

Message: 53121    Hi All,

 

             Please ignore me if I am wrong ,Is this right patch to change the frequency of SCLK and CCLK

             (http://download.analog.com/27516/trackeritem/1/2/3/1232/clksetup.patch).

 

regards,

Outcomes