2008-03-20 12:54:58     Question about BF537 DMA priorities

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2008-03-20 12:54:58     Question about BF537 DMA priorities

Frank Van Hooft (CANADA)

Message: 52850    I've been reading the forums & wiki & the HRM but I don't seem to have a full handle on this yet. I'm hoping someone can give me a pointer in the right direction. I'm using a BF537-STAMP with 2008R1 and I'm receiving 16-bit data into the PPI port at 12.5 MHz. I receive about 400,000 16-bit words, 5 times a second. So, basically I receive 400k words into external SDRAM which takes about 32 ms (ie 400k / 12.5M) then I wait for 168 ms and the process repeats itself.

 

When the PPI DMA transfer completes an IRQ is triggered which turns off the DMA controller & PPI port. So I know they're not running when they shouldn't be.

 

Normally this all works very well.

 

However sometimes, in my error-checking code, I see a PPI FIFO overflow has occurred. I presume this is because the PPI DMA controller was briefly stalled by a higher-priority access to external SDRAM. The documentation shows that by default the PPI has the highest DMA priority of the peripherals, so I presume the only thing that could stall it would be the CPU core. Is this correct? And if so, is there anything I can do about it?

 

Thanks a lot.

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2008-03-20 13:08:30     Re: Question about BF537 DMA priorities

Michael Hennerich (GERMANY)

Message: 52852   

See here:

 

http://docs.blackfin.uclinux.org/doku.php?id=ppi#troubleshooting

 

-Michael

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2008-03-20 13:16:00     Re: Question about BF537 DMA priorities

Frank Van Hooft (CANADA)

Message: 52853    Funny - I'd read that page but never noticed that note. Thanks Michael - I'll give it a try.

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