Setting the PLL mode for the ADAU1701 at different sample rates

Document created by BrettG on Aug 1, 2013
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     The 1701 's fundamental clock is the MIPS clock, which always operates at 49.152 MHz (roughly 50 MIPS) for any "standard" sample rate (48 / 96 / 192 KHz).  The only exception is 44.1 KHz and its multiples, in that case the chip runs about 8% slower, at 45.1584 MIPS.  You're running a standard sample rate (192 KHz), so your -1701 operates at 49.152 MHz.


     As you know, the base 48K sample rate allows for 1024 instructions.  48000 times 1024 equals -- guess what, the 49.152 MIPS rate.  Switching to  192 KHz allows for only 256 instructions, because 256 x 192000 still equals 49.152 MHz.  The chip doesn't run any faster, so you must trade off some program capacity for sample rate.  You set the tradeoff in SigmaStudio's hardware config screen, which in turn sets the core control register in the -1701.  No hardware pins change at all.  That's why your eval board, with its 12.288 MHz crystal, PLLMODE0 = GND and PLLMODE1=3.3V, can run at any of the standard sample rates.


     What the PLLMODE0 and PLLMODE1 pins allow for is the use of different external clock frequencies if desired.  This directly sets the PLL multiplier, so the MIPS clock remains at roughly 50 MIPS with the different MCLK inputs.  Figure 12 on page 18 of the ADAU1701 data sheet would be a bit less confusing if set up as below:



Note that earlier on Page 18, ADI recommends that when using the crystal oscillator, you always  use a 12.288 MHz crystal for standard rates (or 11.2896 MHz for 44.1 KHz rate).  To get your ~50 MIPS clock, you set  PLLMODE0 to 0 & PLLMODE1 to 1 which runs the PLL at MCLK x 4. (or 256 x 48000).  Thus, when using the internal crystal oscillator, there's no need to deviate from what's on the evaluation board -- whether your sample rate is 48, 96, or 192 KHz.


     Best regards,




This FAQ was generated from the following discussion: a dummy question about pll in 1701