How do we limit the MCLK Output frequency on the HDMI Receivers?

Document created by PaulS Employee on Mar 21, 2013Last modified by Sz.O on May 23, 2016
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Using the LIMIT_MCLK_OUTPUT_FREQUENCY.XLS file in the link below, it is possible to limit the minimum and maximum MCLK output frequencies from the HDMI receivers. For example, select the desired maximum output clock from column D and then perform the corresponding I2C writes to registers 0xD4[3:0] and 0xD5 in the DPLL map. Similarly for the lower frequency limit, select the desired minimum output clock from column D and then perform the corresponding I2C writes to registers 0xD3 and 0xD4[7:4] in the DPLL map.

 

This table can be used for the following HDMI Receivers:

ADV7610, ADV7611, ADV7612, ADV7619, ADV7850, ADV7623, ADV7622, ADV7842, ADV7844.

 

Link to the LIMIT_MCLK_OUTPUT_FREQUENCY.XLS file:

http://www.analog.com/media/en/engineering-tools/design-tools/ADV7xx_Limit_MCLK_Output_Frequency.xlsx

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