ADV7850 OUTPUT SYNCHRONIZATION SIGNAL POSITIONING

Document created by Schang Employee on Sep 23, 2012
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The user can reposition the synchronization signal output from the regenerated input synchronization signal within the CP block with the control bits as below:

 

• start_hs[9:0]

• end_hs[9:0]

• start_vs[3:0]

• end_vs[3:0]

• start_fe[3:0]

• start_fo[3:0]

 

Before adjusting the parameters please make sure the following control bits are set correctly:

 

  1. HDMI_MUX_EN(0x1F[4], IO Map) to 1’b0
  2. CP_complete_bypass(0xBF[0], VFE Map) to 1’b0

 

Steven

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