FAQ: Layout recommendations for uPMU/PMU

Document created by LucaV Employee on Aug 8, 2012Last modified by AndyR on Aug 8, 2012
Version 2Show Document
  • View in full screen mode


Do you have specific recommendations when designing a layout for your uPMUs/PMUs?





Typical recommendations given for switching regulators and LDOs apply well in uPMUs or PMUs. It is important to consider each regulator available as a stand-alone unit, this is the reason dedicated power ground and input supply pins are provided to improve bypassing and minimize electrical noise. The input capacitor, especially in buck regulators, must be placed as close as possible to the respective PVIN and PGND. In buck regulators the input capacitor needs to supply a high level of current in a very short time, if the traces connecting the input capacitor to the regulator are long, the parasitic inductance will radiate noise due to the high di/dt signal, this is even more critical in switching regulators operating at high switching frequencies. Inductor and output capacitors need to be placed as close as possible to the uPMU although it is not as critical as the input capacitor circuit, since the inductor carries a constant current plus a certain ripple (assuming the buck regulator is operating in CCM, Continuous Conduction Mode). One potential issue for the inductor is that the residual magnetic flux can couple with nearby components, if this can affect other circuits operation it is recommended to use shielded or ceramic multi-layer inductors and make sure that the PCB layer just below the component layer is dedicated to the ground-plane so it can better shield traces below, it also helps to improve power dissipation when the exposed pad (in LFCSP packages) is connected to the ground plane with multiple thermal vias. One specific issue with uPMU and PMU is the concentration of power and components in a small area, one temptation is to spread the passive components around however it is always better to keep these components as close as possible to the device, Anlog Devices datasheets show typical layout implementations using the smallest components that can fit the requirements, I suggest to follow closely the proposed implementation, we are happy to provide suggestions for special cases that cannot follow the proposed guidelines.


This FAQ was generated from the following discussion: Layout recommendations for uPMU/PMU