ADSP-21469 DDR2 controller-  How to configure bit 0 of the DDR2CTL3 register

Document created by Mitesh Employee on Feb 7, 2012
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In the the current version of the ADSP-214xx HRM (Rev 0.3) and the include file "def21469.h" available with VisualDSP++5.0 update 10 , bit 0 of the DDR2CTL3 register is named as DDR2DLLEN. Actually, setting this bit disables the DLL and clearing this bit  keeps the DLL enabled. DLL should be enabled for proper operation of the DDR2 controller i.e. bit 0 of the DDR2CTL3 register should be CLEARED.  This is planned to be fixed in the next HRM and VisualDSP++5.0 update. The latest revision (rev 5) of the ECG plugin (EE-322) already takes care of this.

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