Trouble Transferring16-Bit Data on Blackfin SPORT

Document created by jobo23 Employee on Nov 30, 2011
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Q: We are using the BF533 and BF561 Blackfin processors in our project, and we cannot seem to transfer data over the SPORT data transmit pin DT0PRI when we configure the SPORT for 16-bit data or smaller. No data comes out at all!  The same code works fine if the SPORT is configured for 17-bit data or larger, as the data is seen on the DT0PRI pin as expected. We are using core loads to the SPORT FIFO in C, as follows:


short myData[4] = 0x0001, 0x0002, 0x0003, 0x0004;

volatile char i;


for (i = 0; i < 4; i++)

   *pSPORT0_TX = myData[i];


Can you explain what we are doing wrong?



A: The SPORT data registers (SPORTx_TX and SPORTx_RX) are the only registers in the Blackfin memory map that must support both 32-bit and 16-bit accesses, and the correct access width is dependent on the SLEN field in the SPORTx_TCR2 register. It is on the programmer to access the MMR with the correct width. The C headers that are provided with the tools set up macros to define the proper access widths for all the registers in MMR space, but this is not possible when the width can be either. As such, the default pSPORT0_TX macro is defined to support a 32-bit access, but we've provided special alternate macros to support 16-bit access to the same MMR address. If you look in the header file for your processor (e.g., the cdefbf561.h file for the BF561), you will see how the SPORT data registers are defined:


#define pSPORT0_TX         ((volatile unsigned long *)SPORT0_TX)
#define pSPORT0_RX        ((volatile unsigned long *)SPORT0_RX)
#define pSPORT0_TX32     ((volatile long *)SPORT0_TX)
#define pSPORT0_RX32     ((volatile long *)SPORT0_RX)
#define pSPORT0_TX16     ((volatile unsigned short *)SPORT0_TX)
#define pSPORT0_RX16     ((volatile unsigned short *)SPORT0_RX)


The "long" type creates a 32-bit access, whereas the "short" is a 16-bit access. You need to use the macro with the "16" suffix for 16-bit data and smaller. What is happening in the hardware when you have the 32-bit access is that the write is not making it to the FIFO because it is misaligned, so when the SPORT is enabled, there is nothing in the FIFO and nothing is transmitted.