AD193x family - supporting Sample Rates lower than 32 kHz

Document created by ColemanR Employee on Aug 15, 2011Last modified by ColemanR Employee on Jun 20, 2012
Version 2Show Document
  • View in full screen mode


I am using AD1937, I need to 8kHz sampling frequency application with AD1937 but first page in the manual  said that it supports 8kHz to 192kHz.

But I can't find how to set register to use for 8kHz.

How can I set AD1937 to support 8kHz?




Many customers would like to run the AD193x family of codecs, ADCs and DACs at sample rates (Fs) that are lower than the standard frequency window of 32 kHz – 192 kHz; the AD193x family has been designed with many alternate functional modes in mind.

In order to use the AD193x at these lower sample rates, an MCLK of 512 x Fs must be provided at the MCLKI port. In addition, the ADC and DAC clock source bitfields must be set to MCLK, instead of the default PLL; the PLL in the AD193x family will not run properly at sample rates lower than 32 kHz and can be powered down. This mode is called Direct Clocking; the Fs is divided down directly from the MCLK frequency. The BCLK frequency remains 64 x Fs.

The part can be used in both Master and Slave modes while using the Direct Lock feature.

AD193x Direct Clocking register settings:

PLL Clock Control 0: Address 0x00

               Set to: 0x81 (Enable Master Clock, Power-down PLL)

PLL Clock Control 1: Address 0x01

               Set to: 0x03 (Select MCLK as clock source for *both* ADC and DAC clocks)

Applicable parts:

AD1933 Diff-out 8-ch SPI control DAC

AD1934 Single-ended out 8-ch SPI control DAC

AD1937 Diff-out 4/8-ch I2C control Codec

AD1938 Single-ended out 4/8-ch SPI control Codec

AD1939 Diff-out 4/8-ch SPI control Codec

AD1974 4-ch SPI control ADC


This FAQ was generated from the following discussion: AD1937 - does it support 8kHz