214xx processors: pull down resistor at SPI_CLK(DPI3) pin may result in SPI master boot failure

Document created by Mitesh Employee on Aug 12, 2011
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The processor when configured for SPI master boot mode uses mode 3 ( CLKPL=1, CPHASE= 1) SPI configuration. In this configuration, the SPICLK is supposed to stay HIGH during idle time. Adding a pull down resistor may produce an erroneous rising edge as shown in the waveform below(Pink-SPI_FLG0_O or DPI5, Green-SPI_CLK or DPI3).

 

spi_boot.JPG

The chip select signal going  low little before this erroneous rising  edge may lead to boot failure as the read command may not be recognized  by the FLASH device proprerly. Thus, it is recommended to either leave the signal SPI_CLK(DPI3) floating or add an external pull up resistor.

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