Document created by sripad Employee on Jun 7, 2018Last modified by Vinod on Aug 1, 2018
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What are the key specification of ADRV9008/ADRV9009 chip?


Key features are as follows:

  • 2T2R1ORX configuration
  • The supported frequency ranges from 100MHz to 6GHz.
  • The bandwidth supported is 200 MHz instantaneous bandwidth and 450 MHz synthesis bandwidth.
  • 6dB lower LO Phase Noise over previous generation
  • -131 dBc/Hz @ 1 MHz offset (1.9 GHz)
  • Low power: 3.8W (50% Rx/Tx)
  • 288 Gbit/s JESD204-B interface
  • Embedded ARM
  • 14 bit ADC, 16 bit DAC
  • 1 RF PLL and 1 Aux PLL for LO generation.


Will the ADRV9009 chip support both TDD and FDD operation?

  1. No, it supports only TDD as there is only one RFPLL which serves as the LO for both TX and RX. For FDD you need to use AD9008-1 and         ADRV9008-2


Where can I find datasheet user guide and schematics for ADRV9008-1, ADRV9008-2 and ADRV9009?

  1. User Guide and other design files can be downloaded from :    

  1. The datasheet can be found from the product pages


What are the evaluation kits for ADRV9008/9?

  • ADRV9009-W/PCBZ: Evaluation kit for ADRV9009 (Dual RF Rx/Tx/Orx Evaluation Board)
  • ADRV9008-1W/PCBZ: Evaluation kit for ADRV9008-1 (Dual RF Rx Evaluation Board)
  • ADRV9008-2W/PCBZ: Evaluation kit for ADRV9008-2 (Dual RF Tx/Orx Evaluation Board)


What all will be in package when I order the ADRV9008/9 evaluation kit?

  1. ADRV9008-1W/PCBZ orADRV9008-2W/PCBZ or ADRV9009-W/PCBZ radio card
  2. Two 8GB SD cards
    1. One for Linux driver and IIO Scope (AD-FMC-SDCARD)
    2. One for Windows-based GUI (ADRV9009-SDCARD)

Note: the package does not contain the EVAL-TPG-ZYNQ3 motherboard which is necessary for operation and must be ordered separately.


What is the difference between ADRV9009 and ADRV9008-1/2

  1. ADRV9009 is single chip optimized for TDD application, ADRV9008-1 is RX chip and ADRV9008-2 is TX & ORx (observation signal path) chip, a two chip solution for FDD application.


Is ADRV9009 pin compatible with ADRV9008-1/2?

  1. Yes it is pin compatible but pins corresponding to sections not used or available on chip needs to be taken care in design.


Where can I get links for ADRV9008/9 evaluation software?

  1. TBU


What is the range of the input frequency to the reference clock pin and its requirements?

  1. The frequency range of the REF_CLK signal must be between 10 MHz and 1000 MHz
  2. The external clock is used as the reference clock for the RFPLL and the Clocking PLL on the device and thus needs to be a very clean clock source. The inputs are biased on the device to a 618 mV voltage level.
  3. Ensure that the external clock peak-to-peak amplitude does not exceed 2V, for phase noise requirements refer UG


Does ADRV9008-1, ADRV9008-2 support MC-GSM.

  1. Yes it supports MC-GSM but requires external LO to meet 3GPP spec in case of RX, It meets the module level requirements, and validation report is not available. For details on GSM use case refer UG.


Does ADRV9008-1, ADRV9008-2 and ADRV9009 support internal DPD?

  1. ADRV9008-2 and ADRV9009 does not supports internal DPD but It has Observation path with bandwidth of 450MHz for external DPD


Will ADRV9008-1, ADRV9008-2 and ADRV9009 support 5G?

  1. Yes, the parts do support most use cases of 5G except that the minimum time required to collect real time signal data to run tracking calibration is 500Usec.


How many RF synthesizers are on board ADRV9009?

  1. 1 RF PLL and 1 Aux PLL. Aux PLL only connects to ORX and is used for calibrations.


What is a stream processor and what is the purpose of that?

  1. The stream processor is a processor within the Talise device tasked with performing a series of configuration tasks upon an external request. Upon a request from the user, the stream processor performs a series of defined actions defined in the image loaded into the stream during device initialization.
  2. The stream processor therefore has “streams” (series of tasks) for:
  • Tx1 Enable/Tx1 Disable, Tx2 Enable/Tx2 Disable
  • Rx1 Enable/Rx1 Disable, Rx2 Enable/Rx2 Disable
  • ORx1 Enable/ORx1 Disable, ORx2 Enable/ORx2 Disable

The stream is not limited to path enabling events and can also react to other events such as a GPIO input signal. The stream processor image needs to be changed with every different configuration. It is recommended to use TES GUI and generate stream file for required configuration.


This was added to make sure the signal path is not disrupted when ARM crashes and still the link is available with reduced performance as tracking calibrations are not running.


What is the purpose of ADC stitching in observation receiver?

  1. The observation receiver signal path allows for an ADC stitching mode. The stitching mode allows for ORx1 and ORx2 digital data paths to be combined to create larger observation receiver bandwidths. Bandwidths of 450MHz are possible by operating in this mode. In this use case, the ADCs are provided with the same signal, i.e. if ORx1 is selected, this input is digitized by all 4 ADCs. For higher bandwidths this mode is selected automatically in profile and any one observation path can be used.


Can I use ZC706 Xilinx board as my base platform?

  1. Yes it is possible but not for all data rates and profiles as the speed supported on GTX is less for ZC706, so it is recommended to use EVAL-TPG-ZYNQ3 board for full compatibility with ADRV900X transceiver. Please note ADI only supports the use of EVAL-TPG-ZYNQ3 with the FPGA image and the evaluation software provided by ADI. Comparison is listed as below



FPGA part no.

Speed grade

Package type

GTX speed supported (Gb/s)


XC7Z045 FFG 900 -2





XC7Z045 FFG 900 -3





Below is the snippet from datasheet showing supported speed for GTX


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