FAQ: "How do I configure the SRAM memory in ADuCM302x or ADuCM4050?"

Document created by Narsimh Employee on Apr 12, 2018Last modified by Narsimh Employee on Apr 24, 2018
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The ADuCM302x and ADuCM4050 ultra low power microcontrollers from ADI offer a configurable SRAM memory that can be partitioned in to data SRAM (DSRAM) and instruction SRAM (SRAM) regions of different sizes. Additional flexibility is offered of enabling an on-chip cache memory by reserving 4KB of SRAM for the same. On-chip cache memory is a unique feature that can be advantageous in lowering microcontroller current consumption and improving performance for certain kinds of embedded code that require repeated access to the same instructions - for example, when running an FFT algorithm on the MCU. For more details on the benefits of enabling on-chip cache memory, refer to the chapter on cache memory in the respective MCU user guides, for example UG-1091 for ADuCM302x. 

 

The tables below provide a summary of the SRAM configuration modes available in ADuCM302x and ADuCM4050. More detailed memory maps with address ranges can be found in the Memory Architecture section of the Introduction chapters of the respective HRM (Hardware Reference Manual) documents that can be found on the product web pages. 

 

Table. 1A: Summary of SRAM configuration modes available in ADuCM302x

 

Mode 0Mode 1Mode 2 Mode 3
CacheN.A4 KBN.A4 KB
ISRAM32KB28KBN.AN.A
DSRAM32KB32KB64KB60KB

 

Table. 1B: Summary of SRAM configuration modes available in ADuCM4050

 

Mode 0Mode 1Mode 2 Mode 3
CacheN.A4 KBN.A4 KB
ISRAM32KB28KBN.AN.A
DSRAM96KB96KB128KB124KB

 

The flexibility offered as described above, empowers developers to tailor the microcontroller SRAM memory depending on their application. For example - certain condition based monitoring or healthcare wearable applications that require storing large amounts of sensor data in SRAM can opt for Mode 2 or Mode 3 that reserve most of SRAM for storing data (up to 64KB in ADuCM302x and 128KB in ADuCM4050). Applications that are algorithm heavy and/or can benefit from having some or all of their code executing from SRAM, can opt for Mode 0 or Mode 1, where a large chunk of SRAM is reserved for instruction SRAM ( up to 32KB in both ADuCM302x and ADuCM4050). 

 

Users can configure appropriate SRAM mode by modifying the linker file in their embedded projects. For this - the recommended method is to make a copy of the default linker file provided with the device drivers (DFP). Using IAR embedded workbench as an example (similar applies if using CCES or Keil), the default linker file - for example 'ADuCM4050-flash.icf' would be available in the DFP installation directory at a path that would be similar to:  C:\Users\<user-name>\AppData\Local\ IAR Embedded Workbench\PackRepo\AnalogDevices\ADuCM4x50_DFP \3.1.1\ARM\config\linker\AnalogDevices\ADuCM4050-flash.icf.  Copy this .icf linker file in to your project directory and configure IAR to pick up this local linker file (see snapshot below). 

 

 

Edit this local copy of the linker file to select the SRAM configuration mode. For this - search for the USER_SRAM_MODE variable in the linker file (see snapshot below) and edit the value to suit your requirement.

 

 

In case selecting USER_SRAM_MODE 2 or 3 (ISRAM disabled), it is also required to use the #define ADI_DISABLE_INSTRUCTION_SRAM macro in the startup_ADuCMxxxx.s and startup_ADuCMxxxx.c files in your project. 

 

In case selecting USER_SRAM_MODE 1 or 3 (Cache enabled), it is also required to use the #define ENABLE_CACHE macro in the startup_ADuCMxxxx.c file in your project. 

 

And with this - you should be all set to compile your embedded project and take advantage of the flexibility provided in configuring SRAM.

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