AD936x documentation changes

Document created by srimoyi Employee on Mar 23, 2018Last modified by srimoyi Employee on Mar 23, 2018
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This document captures the documentation changes planned for User guide and Register map for AD9361, AD9363 and AD9364 Radio Verse Transceivers. Document update and release will take time and until that time this document will be maintained for reference.


Current version of documents is as given below. If you don’t have the latest, please download same from design file package under below link.






Data Sheet

Rev F

Rev D

Rev C

User Guide

UG-570 REV A

UG-1040 REV 0

UG-673 REV 0

Register Map

UG-671 REV 0

UG-1057 REV 0

UG-672 REV 0


Below table captures the changes required for documents and their reference. If you have any comments or suggestions to improve documentation, please feel free to post your comments below.




Sl No


Current statement



UG-570-page 95 to 96, UG-1040-page 79 to 80


Headings and timing diagrams for receive or transmit data needs to be corrected.

Refer appendix A.


UG-570-page 8 equation:1

UG-1040-page 7 equation:1

UG-673-page 7 equation:1

There is no definition of the term “Divide Setting”.

To be included.



UG-673-page-100 table 53 (for LVDS)

Column 2 of table 53 mentions data rate as 122.88 Msps

Data rate needs to be changed to 61.44Msps.

The term “combined I and Q words”

is to be removed.


Reference manuals of all versions of Catalina

Ball J6 "CLK_OUT" has multiple name aliases including "CLOCK_OUT", "CLKOUT" and "CLK Out"

CLK_OUT naming convention to be followed



table 48


table 47


table 51

In CMOS mode in DDR TDD mode, sample rate can be up to 122.88M instead of 61.44M.

Refer appendix B

The term “combined I and Q words”

is to be removed.


Required for all register map

Rise in image frequency at higher power levels. Increase in correction word decimation, i.e., Register x16F (registers x16C-x16F) have been removed from the register map.

Refer appendix C





Register 0x20 = 0x24(toggle the GPO_1 pin in Rx and GPO_2 in Tx)






Register 0x20 contains the bits that determine how the GPOs respond to state changes from Alert


If 0x20=0x24,

From alert to RX, GPO will go from 0xF to 0x2 (3 GPOs will toggle)

From alert to TX, GPO will go from 0xF to 0x4 (3 GPOs will toggle).


Register 0x20 defines the "state" or value of GPO upon entering RX or TX state.

8      A calibration can reduce the uncertainty of the temperature sensor reading but even with a calibration, there is   significant uncertainty and the sensor should only be used for non-critical functions. A document explaining that is     given in the link:


9       Signals closer than 7.5 kHz to DC and which are large in the digital domain can cause the DC offset algorithms to remove those signals, affecting the algorithm and the desired signals. A document explaining that is given in the link:






Datasheet of AD936X

In the reference clock voltage specification, move the 1.3V pk-pk value to the max column instead of putting it in the typical columns of the specs table (Adding a comment that lower values can degrade performance)

To be updated


Table 13 of AD9361 datasheet, 

Table 12 of AD9363 datasheet,

Table 13 of AD9364 datasheet

All Rx and TX data pairs have optional termination

Remove the termination text from RX_Dx_p/n and Termination needs to be added to the definition for FB_CLK and TX_FRAME.


Page 18 of AD9363 datasheet

The description of pin no J6 states: ”This pin can be configured to output either a buffered version of the external input clock (the digital controlled crystal oscillator (DCXO)) or a divided down

version of the internal ADC sample clock (ADC_CLK)”.

The words“(the digital controlled crystal oscillator (DCXO))” are to be removed. The AD9363 only allows reference injection via pin M12, i.e. XTALN; its neighbor M11 is DNC (in AD9361/64 this is XTALP), so unlike its sister parts, the AD9363 does not support the DCXO option.









Applies to the fast AGC. The AGC Attack Delay prevents the AGC from starting its algorithm until the receive path has settled

Applies to slow and fast AGC.


UG-671-page-65 and 60, UG-1057-page-63 and 68,UG-672-page-60 and 65

In registers x238 and x278 we need to put VCO Cal Offset back into the register words, those were zero-ed out by mistake.

To be updated


UG-671-table 9,

UG-672-table 9,

UG-1057-table 9

For ADC_CLK /2 and ADC_CLK/3 works fine but for ADC_CLK/4 onwards it gives wrong clk_out as after MUX 1, output is routed to HB3 clk.

Table 9 needs to be updated as in appendix D


UG-671-table 84

UG-672-table 84,

UG-1057-table 83

If tones are injected in RX, the mask bit always flips the IQ i.e. if I is masked Q samples are zero.

Naming convention needs to be changed in reg map document register 0X3F6


UG-671-page 18,

UG-1057-page 20,

UG-672-page 18

The register definitions (0x03c, D5) refers to the setting as "Rx On Chip Term" and say all data path bits plus TX_FRAME and FB_CLK.

That needs to be changed from the "all data path pins" to TX_Dx_p/n pins.


UG-671-page 33


Resolution: 1pF/LSB. Total capacitance is 12pF + Capacitor<5:0> *1pF (required for the calculation of 3db cut off frequency)


To be updated


UG-671-page 15

UG-672-page 15

UG-1057-page 15

This nibble controls which GPO_x pins change state when the ENSM enters the Rx state

It defines the "state" or value of GPO upon entering RX or TX state.


UG-671-page 60 and page 65

UG-672-page 60 and page 65

UG-1057-page 63 and page 68





For register 0x23D and 0x27D,Bit [D5] in the reg map is an “open” bit.

Bit [D4] however, is described as “CP Offset Off Setting this bit disables the charge pump bleed current.  Clear to use the value in “Charge Pump Offset” (0x23C[D5:D0]) as the offset current.”


CP offset current needs to be disabled by setting the CP Offset Off bit (0x23D[D5] for Rx and 0x27D[D5] for Tx)














Above document captures the changes required for documents and their reference. If you have any comments or suggestions to improve documentation, please feel free to post your comments below.

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