The AD7768/AD7768-4 outputs data as a master, meaning that the device continuously streams data and it is the user's task to read the data as it is output. Therefore the microcontroller that interfaces to the data output lines must be configured as a slave. (A separate interface needs to be configured if SPI control is required. If not, the AD7768/AD7768-4 can operate in pin control mode)
The AD7768/AD7768-4 data interface has been tested by reading data using the Serial Audio Interface (SAI) on a microcontroller. For this example all 8 channels of AD7768 were output on DOUT0.
The connections required for the data interface on the AD7768 side are:
- DRDY - this is the flag that signals new data is ready to be read.
- DCLK - this is the data output clock.
- DOUTx - this is the pin the data is output on. The AD7768 can output data on 1, 2 or 8 DOUT pins. The AD7768-4 can output data on 1 or 4 DOUT pins. DOUT0 was used for this test case.
The connections required to the microcontroller are:
- FS (frame start). Used to signify a new conversion result is being output by the AD7768/AD7768-4. Connect this pin to DRDY on the AD7768/AD7768-4
- SCLK (the interface clock) Used to clock the data into the microcontroller. Connect this pin to DCLK on the AD7768/AD7768-4. The master supplies the clock for the transaction, DCLK in this case. DCLK on the AD7768/AD7768-4 can be configured as a divided down version of the master clock (MCLK).
- SD. (Serial data input) In the case where one DOUT is being used, this pin needs to be connected to DOUT0 on the AD7768/AD7768-4.
Configuring the Interface
The microcontroller interface needs to be configured to accept the data output from the DOUT pins. For this example, all 8 channels of data are output on DOUT0 for the AD7768. Data is being read on the SAI interface which is configured as follows:
- Configure the SAI as an asynchronous slave
- Set the frame length to 256 bits. Data size is 32 bits. (32 bits x 8 channels = 256 bits total every DRDY)
- Save data to 8 slots, each of 32 bit size
Configuring the AD7768
- On the AD7768 configure FORMAT0 and FORMA1 pins to logic 1. This outputs all data on DOUT0.
- Set the DCLK frequency to MCLK/1
- The output data rate (ODR) can be set from the slowest possible rate up to 128kHz. If the max ODR of 256kHz is needed, two DOUT pins must be used to read all the data.
Note: On the AD7768-4 since there are only 4 channels the same constraint does not apply.