FAQs: DAC Communication Troubleshooting

Document created by rrosario Employee on Oct 20, 2017
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Q: I’m trying to communicate with ADXXXX but the output doesn’t respond to the commands?

A: Take an oscilloscope shot of your digital lines and check the following items:

  • CPOL & CPHA of the SPI interface : The Serial Peripheral Interface (SPI) follows 4 different transmission modes for the data. CPOL describes the default state of the clock, meanwhile CPHA which edge of the clock will the data be valid. You may refer to AN-1248 for a more detailed discussion on SPI transmission modes.

 

 

  • Timing Specifications : Violation of any of the timing parameters described in the data sheet will cause the part to not respond to the command. In signal generation applications wherein we want to minimize the time to update the output, we tend to operate the part outside of the timing specifications. One timing that is usually reduced is the SYNC high time to generate the next write sequence immediately. When the SYNC high time is lower than specified minimum specification, the device might interpret it as an invalid SYNC high and not perform the command or the device might not be able to perform the internal calibrations and cause some errors in the output.

 

  • Write/Read SequenceWrite (Sample thread) : Some devices have a recommended programming sequence upon power-up like the AD5410/20 before writing to the DAC registers. See Figure below:A reset command triggers a power-on reset event to ensure the proper operation of the device. The POR allows the device to initialize to the correct internal calibration registers and for the reference to settle to its correct trim value.

 

Read : some DACs have the SDO pins disabled by default. The AD5754 is one of the of these devices which has the capability to disable the SDO pin.

 

  • Logic Levels : The logic levels of the digital lines should comply to the minimum or maximum levels specified on the data sheet. The logic levels of the microcontroller/DSP should match the logic levels required by the device. The logic levels are dependent on the device logic supply. On this sample thread , the user is dealing with the AD5761R with the VLOGIC and VDD both connected to a 3.3V supply and a microcontroller with a 3.3V logic interface. There are no issues with the communication until he wanted the DAC to output a voltage greater than 3.3V so he increased the supply to 5V. Reviewing the logic level specifications of the AD5761R below.

   

         The customer needs 0.7xVLOGIC for a HIGH to have a valid communication with the AD5671, so when 5V is connected VLOGIC pin, the logic “HIGH” should be 3.5V at a minimum to have a reliable communication interface. Possible workaround for this is to use a level translator to increase the “HIGH” voltage or decrease the supply to the VLOGIC pin to match the microcontroller interface.

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