FAQ: ADF4153 DLD ( Digital Lock Detect )

Document created by enash Employee on Feb 3, 2011Last modified by AndyR on Jan 31, 2012
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Why doesn't DLD (Digital Lock Detect) work on the ADF4153 for PFD frequencies higher than 15MHz?




For PFD frequencies higher than 15MHz the accuracy of digital lock detect is compromised. The reason for that is that the period of high pfd frequencies gets close to the digital lock detect window. Taking for example an application that uses a Fpfd = 28Mhz, the period is around 35ns. The DLD window is 15ns. In an unlocked state the phase error is very low and might not get outside the 15ns window.

The only solution is to either decrease Fpfd or use Analog Lock Detect.


This FAQ was generated from the following discussion: ADF4153 DLD ( Digital Lock Dectect )