FAQ: How to synchronize multicores with TRU or Interrupt?

Document created by Jithul_Janardhanan Employee on Aug 29, 2017Last modified by Jithul_Janardhanan Employee on Sep 19, 2017
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Overview: This document explains how to synchronize multicores with TRU or interrupt on ADSP-SC5xx/215xx processors.

 

Interrupts provide a reliable synchronization medium as they are serviced through the processor core. However, interrupts can add latency due to the time needed for core detection, context saving, and event servicing. The event processing latency depends on many conditions, such as priority levels or handling of simultaneous interrupts.


Whereas the TRU provides system-level sequence control without core intervention and helping reduce the delays involved in the synchronization process, as it removes the core processing of the event and increases determinism. Therefore, the TRU provides an efficient alternative to core interrupts for event synchronization in embedded systems. The TRU maps trigger masters (generators of triggers) to trigger slaves (receivers of triggers).

 

Attached are the code examples for multicore synchronization with TRU and Interrupt. Considering the code example ‘TRU_Interrupt’, a pin interrupt trigger master from SHARC Core1 is used to trigger a slave for interrupt request for SHARC Core2. The ‘TRU0_SLV8 (Core 2 only)’ is used as the TRU interrupt and the handler for this is written in the SHARC Core2. This TRU interrupt is triggered by the PINT5 master trigger configured in the SHARC core1. The advantage of using TRU is that we need not to write ISR for PINT, thus it saves the delays mentioned above.


The table below provides the ADSP-SC58x TRU Interrupt List.

 

When executing this code in ADSP-SC589 EZ-Kit, once you press the PB1 gives master trigger (configured in SHARC_CORE1) to TRU0 interrupt 8 (configured in SHARC_CORE2) . This will navigate the control to it handler where the LED gets toggled.


“When using the GPIO trigger masters for back to back triggers, the trigger assertions latched in the corresponding latch registers (PINT_LATCH) must be cleared in software for back to back triggers to work

 

Now, consider ‘Mutlicore_Sync_Interrupt’ example code. It uses Interrupts which are a common way of synchronizing operation between events. On the SHARC core1, inside the PINT5 interrupt handler a software interrupt for SHARC core2 is generated (INTR_SOFT0). The handler for software interrupt is written in the SHARC core2 and it executes an LED toggling. For better understanding refer the comments embedded within the example code.

 

The third example "TRU_MulcoreSync_Timer_Interrupt", demonstrates how a periodic timer synchronizes both SHARC cores of ADSP-SC58x. A general-purpose timer (GP Timer0) in SHARC Core1 is configured to generate a continues pulses and configured this as Master trigger. Note that the TMR[nn] bit in the TIMER_TRG_MSK register, when write =0 unmasks (enables) the corresponding data trigger output.

 

The ‘TRU0_SLV4 (Core 1 only)’ is used as the trigger slave for SHARC Core1 and the ‘TRU0_SLV8 (Core 2 only)’ is used as trigger slave for SHARC core2, which provides TRU interrupts. The interrupt handler for TRU interrupt is programmed to toggle different GPIOs in each cores and the TRU interrupt is triggered by Timer0 master trigger upon period expiry.

 

See the attached wave form which are the GPIO output from both SHARC cores 1, you can see that both GPIOs are synchronized by the timer0.

 

For processor specific details, refer to the device Data Sheet and Hardware Reference.

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