ADAS1000 DRDYb operation

Document created by CatherineR Employee on Nov 28, 2016
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The purpose of this document is to describe a little more about the DRDYb operation of the ADAS1000. This should be read in conjunction with the ADAS1000 datasheet descriptions.

There are two modes of interfacing operation within the ADAS1000,

  • read/write registers (standard 32-bit register read/write operation)
  • Frame mode

 

Frame mode

  • Once the device has been configured and ecg conversions enabled, the host writes to the FRAME register to start reading ecg conversion data. The device is now in frame read mode, where the host issues all zeros on the SDI pin and reads the conversion results on the SDO.
    • Any non-zero words on the SDI line during frame reads are understood to either be register reads/writes - where host wants to change the configuration or read some register information. As a result the frame read will be interrupted to allow the device process the incoming command.
  • The ADAS1000 performs data conversions and makes data available at the programmed rate (user programmable 2kHz, 16kHz or 128kHz). The DRDYb function signals data is ready for the host to read.
  • The DRDYb should be monitored as a level sensitive hardware pin, a software bit in the frame header or the level of the SDO. For simplicity, this article will focus on the hardware pin.
  • When the conversion data is ready, the DRDYb pin will be driven low by the ADAS1000, prompting the host to read the conversion result.
  • Once ecg conversions are started, new data will continue to be ready and available to read at the programmed rate, so DRDYb will keep going low to indicate ready status, it is now the job of the host micro to keep reading data at the programmed rate.
  • In the event that a frame is missed, not read completely or not read fast enough for the programmed rate, the DRDYb line will stay low - it stays low waiting for the frame register to be emptied (new results are only written into the frame register if it is empty).
  • The host should always check the level of DRDYb, if it is low, then the host reads a frame of data. If it appears to stay low, then the host should issue another full frame read.
  • The frame header will contain information on whether frames were missed. The frame header contains 2 bits which indicate if there has been an overflow since the last read (missed 1 to 3+ frames). These overflow bits indicate to the host that there has been a gap/break in the data stream. The data read at the time of a frame header with overflow bits set is valid data, it is the latest result.I
  • n the event that DRDYb does not return high, and the device is in frame mode, then the likelihood is a new set of conversion results arrived into the frame register at the same time as the previous read thereby keeping DRDYb low. The host should check again level of DRDYb, if it is still low, then issue clocks for another full frame read.
  • An example flowchart of configure to frame mode is shown below:

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