FAQ: The Ultimate Guide to the ADF5355 Microwave Wideband Synthesizer

Document created by MRichardson Employee on Oct 21, 2016Last modified by MRichardson Employee on Nov 8, 2016
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Since it's release in early 2015, this integrated VCO / PLL synthesizer has been designed into a wide variety of applications and by designers of all levels of expertise. This document attempts to address the more common questions or issues that our customers have encountered while working with the ADF5355 Microwave Wideband Synthesizer. The content contained herein is based on the collaborative efforts of not only myself but many other individuals throughout the global ADI engineering community who have faithfully supported this product over the past couple of years. We trust the information will be of assistance to you as well. The content is arranged alphabetically by topic to simplify navigation.

 

 

ALC (Automatic Level Calibration)

Question: What exactly does this circuit do and can I change the settings manually to improve my phase noise or spur performance?

Answer: The Automatic Level Calibration or “ALC” circuit sets the VCO core bias current for optimum phase noise across the band. The ALC wait time allows the frequency to settle prior to band selection. It’s 2.5x longer than the synthesizer lock timeout. The synthesizer lock timeout has its own timing needs as it must wait for the VCO calibration DAC voltage (Vtune) to settle prior to selecting the proper band. Disabling this feature is not recommended.

 

 

AUTO-CALIBRATION

Question: Do I need to “re-calibrate” the ADF5355 VCO after a change in temperature.

Answer: No, in fact you may degrade the phase noise performance by re-calibrating after the ambient temperature changes. The ADF5355 utilizes a temperature compensated calibration routine so that it will remained locked over the operating temperature range of -40°C to +85°C regardless of the ambient temperature when locked. Typically the initial lock would occur at 25°C which results in good phase noise performance. In order to remain locked, the desired frequency must land at a location within the band that has adequate Vtune margin on either side to allow operation out to the temperature extremes. If the device is first locked (or re-calibrated and locked) at -40°C it will remain phase locked up to 85°C however it will likely suffer degraded phase noise performance due to the higher tuning sensitivity that’s present at the lower tune voltages. If you’re application requires re-locking at temperature extremes please contact the factory to discuss the options.

Question: What is the increase of the RF output power from RF OutA using the pull-up inductor and AC-coupling cap as shown on figure 53 in the datasheet.

Answer: Inductor improves the power on RFoutA by ~1 - 2dB. It appears that the plots include the 7.5nH inductors.

 

Question: If I’m not using RFOUTA, can I ground PDBRF instead of pulling it high.

Answer: If RFOUTA is disabled in software (R6, DB6 = 0), the RFOUTA+ and RFOUTA– pins can be left floating. PDBRF only powers down the RFOUTA pins. The datasheet is being updated to reflect this. PDBRF should not be left floating. 

 

Question: What is theta j-c of ADF5355?

Answer: ADF5355, Theta-JC=0.094°C/W based on 1S0P PCB and 3 x 3 vias.

 

Question: What is the typical max power of ADF53555?

Answer: Typical Max Power dissipation for ADF5355 is (5.0Vdc x 78mA) + (3.3Vdc x 171mA) = 0.954Watts.

 

 

BIASING

Question: Does the ADF5355 have any power sequencing requirements?

Answer: No. Early versions of the datasheet seemed to indicate otherwise but this has been corrected.

 

 

CHARGE PUMP

Question: Can I adjust RSET to vary the charge pump current range (similar to what can be done on some other ADI PLL models)?

Answer: No. Although there is a 5.1kΩ resistor populated at pin 22 (RSET) it actually isn’t doing anything as RSET is internal to the device. This resistor is not actually required.  

 

 

CURRENT

Question: What frequency was used to create Table 6 which illustrates current consumption under various conditions?

Answer: Table 6 is intended to be representative of the nominal current draw and is therefore doesn’t represent a specific frequency.

 

Question: What is the split between DiDD and AiDD; these are shown as a combined value in the datasheet and I would like to separate the digital and analog supplies?

Answer:  Measured performance of a part and noted the combined current was 66mA as opposed to the 62mA listed as nominal in the datasheet but the following should serve as a good reference.

DVdd:16mA,  AVdd1 (pin 5):26mA, AVdd2 (pin 16):24mA. So about 50mA for AVdd and 16mA for DVdd.

 

Question: Why does current consumption only decrease a “negligible amount” when I disable RFoutB?

Answer:  Due to the VCO architecture RFoutB is always on, the “disable” feature only disconnects the RFoutB signal from the pin.

 

 

CREG1 / CREG2

Question: Is it possible to use LDO output CREG1 and CREG2 from ADF5355 to power up any other external circuitry?

Answer: This hasn’t been tested or characterized and is not recommended. It likely would destabilize/degrade the performance of the ADF5355. These are for the digital circuits which are typically noisy anyway.

 

 

DIGITAL LOCK DETECT

Question: Digital Lock Detect (DLD) isn’t always declaring ‘Lock’ but I can see that the frequency is phase locked, why is this?

Answer: The Digital Lock Detect circuitry is robust and should work reliably. In the event that it doesn’t there are a few things to be aware of. First of all, changing lock-detect precision (LDP) from Frac to Int (2.9ns) REG7[4] generally makes things worse unless you’re in INT mode. When it’s set to FRAC the value is given by LD Delay bias in REG7[6:5] and in general the longest or highest delay should be the most reliable in setting DLD high. The down side is that the DLD circuit is slower to respond.

 

 

EVALUATION BOARD

Question: Is a schematic available for the evaluation board?

Answer: Yes, visit https://ez.analog.com/message/165381. Note that there is one error, C15 should be 100nF not 1uF.

 

Question: Can I get the evaluation board CAD files?

Answer: Yes, the CAD work was done in Allegro and the files can be found at this link: https://ez.analog.com/thread/71981

 

Question: What’s the purpose of jumper 3 that is tied to Muxout and LE on the ADF5355 evaluation board?

Answer: This is used during testing of the evaluation board to verify operation.

 

Question: I noticed that the ADF5355 evaluation board has placements for IP5 connectors do you have a part number for these?

Answer: These are typically used for special cases. IP5-04-05.0-L-S-1-TR will mate to the evaluation board while IJ5-04-05.0-L-S-1-TR should be used on any daughter board that would mate to this. Most users won’t need these.

 

Question: After powering up my ADF5355SD1Z evaluation board the output power is low.

Answer: These boards should draw about 265mA ±10mA AFTER programming / writing to the registers. If the current is o.k. be sure that REG 6 is configured properly (RF Output and / or Aux Output are enabled (Rfout A± and RfoutB respectively) and the power level for RFoutA is set to the desired level. If these appear to be o.k. verify that there is 3.3V at the PDRF test point (tied to pin 26). Lastly, verify that the 0201 output components are intact. These can easily be damaged if care isn’t taken while handling the board.

 

 

LOCK PROBLEMS

Question: Unable to lock at very low frequencies (<330MHz) even though I’m using divided feedback (preferred setting when using the output divider) and N>23.

Answer: The problem appears to be related to the use of REG 6 [DB30] set to Gated Bleed: Gate on DLD (Digital Lock Detect). If the problem continues and Digital Lock Detect is being used it may be necessary to either design a loop filter for operation at the lower frequencies (or some compromise that allows operation across your band) or switch to Analog Lock Detect see REG4[DB29:27].

 

Question: What is the proper amount of bypassing on the VBIAS pin?

Answer: Excessive capacitance on VBIAS (pin 24) can result in lock problems. We recommend leaving C28 at 10pF, C26 at 100nF and de-populating C15.

 

Question: In our application we’re experiencing some random lock problems that occur rarely (ppm range) but are still a concern. What's causing this and what can we do to eliminate these lock issues?

Answer: We believe this issue is tied to a glitch that sometimes occurs in the ALC circuitry. Most customers will likely never experience this problem as occurrence is on the order of the ppm range. Assuming all else is o.k., including the loop filter design, no damaged components, traces, proper bypass capacitance at VBIAS pin, and the ALC circuit is enabled along with the default settings shown in the ADF4355 GUI then you can try the following. Some customers have reported improvement by enabling double buffering REG4 [14]. There also may be some improvement through altering the lock detect settings in REG 7. Lastly, you may simply need to re-write the registers a second time.

 

Question: Auto-Cal occasionally fails resulting in the ADF5355 failing to lock. What can I do to prevent this?

Answer: One setting that will degrade phase lock reliability is enabling ‘Loss of Lock’ mode (REG7, DB7) while the REFin mode (REG4[DB9] is set to ‘Differential’ mode. Unless the reference input frequency is greater than 250MHz (regardless of the actual mode that is being used) REG4 [DB9] should only be set to ‘Single' ended mode. This insures that the best spur performance is retained. If spurs are not a concern then the actual physical implementation should be used. Finally, ‘Loss of Lock’ mode is intended for fixed frequency configurations where the reference is likely to be removed such as is the case for certain clocking applications, it only functions when operating the REF input in ‘Single Ended’ mode.

 

 

LOOP FILTER

Question: What can be done to minimize microphonics problems?

Answer: Use NPO / COG grade loop filter components. As a general rule of thumb you should never use capacitors with a temperature coefficient greater than X7R in your loop filter anyway if you want decent loop performance over temperature.

 

 

LOSS OF LOCK

Question: I’m experiencing some locking issues will enabling LOSS OF LOCK help?

Answer: Loss of Lock (REG7, DB7) is intended for fixed frequency applications where the reference clock might be removed or disabled such as clocking applications. It only works with a single ended reference. Use of it with a differential reference, or a single ended reference but in differential mode (REG4, DB9) will result in lock problems.  

 

 

MODELS

Question: Does Analog Devices have an IBIS model for the ADF5355?

Answer: Unfortunately, no. Some customers have been able to use the IBIS model that exists for the ADF4158 and have mentioned that it was close enough. Contact ADI applications for further information.

 

 

MODULATION BANDWIDTH

Question: What is the modulation bandwidth of the ADF5355?

Answer: This is a difficult question to answer and something that we haven’t characterized on the ADF5355. The primary reason being related to the complexity of the Vtune circuitry used to tune the VCO cores. Requirements with small deviations (1MHz or less) have been fine with similar devices like the ADF4350 however these also have fewer bands and more margin. Ultimately customers will need to evaluate this on the bench for their specific requirement if this is important for their application.

 

 

MUXOUT

Question: What is the type of output ADF5333 MUXOUT in "Analog Lock Detect" mode: open-drain or push-pull?

Answer: From the MUXOUT diagram in the datasheet it is a push-pull from DVDD TO DGND.

 

Question: I’d like to use the MUXOUT functionality of the ADF5355 to verify that each internal block of the PLL is operating properly as I verify my code. What should I see when I use these functions?

Answer: The muxout voltage is set in REG4[DB8], this sets the output voltage level to 1.8 V or 3.3 V. Once set the rest is easy. If you set REG4[DB29:27] to send the R divider to the output, then you should get a waveform at your PFD frequency oscillating between 0 V and 1.8 V (or 3.3 V). The N counter output operates similarly except the pulse widths can be very narrow. Digital lock detect (DLD) gives a steady 1.8 V (or 3.3 V) output once the loop is locked.

 

Question: Can I use analog LD on the ADF5355?

Answer: While AN-873 is applicable to the ADF5355, it is not recommended to use analog lock detect (ALD) on the ADF5355 as it can lead to spurs on the RF output. This is because the ALD outputs pulses on muxout. These pulses are the XOR result of the PFD N and R inputs. There is a possibility that the frequency of these pulses appear as a spur on the RF output.

 

 

N- DIVIDER

Question: I’d like to bypass the 4/5, 8/9 dual modulus prescaler so that I’m not limited to N>=23 and N>=75 is there any way to do this?

Answer: Unfortunately this isn’t possible on the ADF5355.

 

 

OUTPUT POWER

Question: I need all the power I can get out of the RFoutA± port (3400MHz – 6800MHz), can I combine these differential outputs with a balun for a single ended solution with increased output power?

Answer: Absolutely, the final output power achieved will depend on the losses of your balun and the amplitude flatness. There are some simple online tools that may be helpful for narrowband designs. Below is an example (the 0402 component parasitics are included in the model but not shown). While we haven’t had a chance to try this out, it may serve as a good starting point.

 

 

 

Question: I need to use the doubled output (RFoutB) for my application but the fundamental feedthrough is an issue. What can I do?

Answer: The fundamental feedthrough that appears as a sub-harmonic (½ harmonic) on RFoutB can easily be addressed by the addition of a high pass or better yet, bandpass filter. The advantage of a good bandpass filter is that the higher order harmonics will be attenuated as well.

 

Question: I’m using RFoutB but I need better power flatness across the 6.8GHz – 13.6GHz frequency range as well as a higher drive level for the next stage in my design? Any suggestions?

Answer: Analog Devices has a wide variety of amplifier products to meet virtually any need you have. Single ended products that cover the full output frequency range (6.8GHz to 13.6GHz) include the HMC441, HMC451, HMC606, HMC659, HMC634 or HMC1089. An analog controlled VGA such as the HMC694 offers additional control but does require negative bias on the control pin. Visit Analog.com or contact ADI applications for more information.  

 

Question: I need a differential output on RFoutB, any recommendations?

Answer: Analog Devices has several single ended to differential amplifier products that may work depending on your frequency range and requirements. Visit Analog.com or contact ADI applications for more information.

Model

Function

Frequency Range

ADL5721

SE to DIFF, LNA

5.9GHz – 8.5GHz

ADL5723

SE to DIFF, LNA

10.1GHz – 11.7GHz

ADL5724

SE to DIFF, LNA

12.7GHz – 15.4GHz

 

Question: How much can I expect the output power to vary due to process variation?

Answer: Typically ±1dBm

 

Question: Typically power decreases with temperature, the plot for power vs temperature indicates that power increases with temperature is this correct?

Answer: Yes.

 

Question: Does PDBRF (pin 26) power down the entire chip and if so how do I make sense of the conditions?

Answer: No, to power down via hardware you’ll use Chip Enable (CE, pin 4) for a software power down you’ll use REG4[DB6]. PDBRF only powers down RFoutA ±.

 

Question: I’m using the evaluation board and the output power on RFoutA is low very low when operating at 250MHz, why?

Answer: That is to be expected and is due to the narrowband match provided by the 7.4nH pull-up inductors. To improve the output power to 5-6dBm replace these with 100nH pull-ups. This is recommended when operating on RFoutA at frequencies below 2GHz.

 

Question: What power level can I expect if eliminate the external 7.4nH pull-up inductors and rely on just the internal 50Ω resistors?

Answer: Using just the internal 50Ω resistor the performance will be lower by about 1-2dB from 3400MHz – 6800MHz (sloping from +2 to +3dBm to -6dBm). However, the power at frequencies below 2GHz should be higher since the resistor is by nature much more broadband.

 

 

PACKAGE

Question: Is the ADF5355 available in die?

Answer: Not at this time; however if a strong enough business case can be made anything is possible. Contact Analog Devices sales or applications for more information.

 

 

PFD FREQUENCY

Question: What Bleed current should I use at higher PFD frequencies?

Answer: Internal testing has shown that the best jitter performance over a 1kHz to 100kHz range was achieved using a bleed current setting of 42 when the PFD frequency exceeds 80MHz.

 

 

PHASE

**Note that to use the phase features, including phase resync, the feedback mux has to be set to "divided". The feedback mux is the one after the VCO that goes to the PLL core (int counter & SDM). It has two settings, in "fundamental" setting the VCO fundamental is always fed back to the PLL core. In this case, the dividers in the output buffer only affect the output frequency. We found that this setting was best for spurs, we used it for all 4355, 5355 & 4355-3 evaluation, unfortunately the phase features don't work properly in this state. By using the "divided" setting the signal from the output dividers is routed to the PLL core and the phase features work properly.

 

Question: Can I adjust the output phase in order to sync a reference clock and ADF5355 output clock by using the phase adjust function?

Answer: Yes but SD Load reset must be enabled and phase adjust does not work in Integer mode as it’s associated with the SD modulator which is only enabled in fractional mode. ADI Fanout buffers like the AD9508 provide a coarse adjustment for phase on the output. Also, phase adjust can’t be used simultaneously with the Phase Resync function on the ADF5355.

 

Question: Is the ADF5355 phase coherent?

Answer: Yes, however there are two conditions. Phase coherency is the ability to retain the initial phase of a signal after hopping to a different frequency and returning to the original signal. This is only an issue in fractional mode. Many PLL synthesizers are unable to provide this level of phase control however the ADF5355 can achieve this using the Phase Resync, REG 3 [DB29] feature as long as FRAC2 = 0 and as long as Phase Adjust, REG 3 [DB28] is not being used at the same time. 

 

 

PRE-RELEASE PARTS

Question: I have some “pre-release” ADF5355 parts and I’m wondering if these are acceptable to use.

Answer: No. The register values in the datasheet are not optimized for pre-release parts. Pre-release parts are no longer supported as the ADF5355 was released nearly 2 years ago. You’ll need to obtain sample of the released ADF5355 parts.

 

 

RELIABILITY

Question: Does ADI have any vibration or G-sensitivity data for the ADF5355?

Answer: No. The primary end applications for this product are commercial in nature and vibration and G-Sensitivity are generally reserved for space and military applications.

Question: The lowest voltage I have available in my application for the 5.0V bias feeds is 5.5Vdc – 6.0Vdc. Can I operate the ADF5355 at this elevated voltage?

Answer: We don’t recommend exceeding the maximum bias voltages listed in the Absolute Maximum Ratings (AMR) table shown in the datasheet. Operation above the nominal values but below the AMR will result in increased power dissipation and some reduced life expectancy due to the slightly higher levels of bias and thermal stress. Users operating above the AMR values do so at their own risk.

 

 

REFERENCE

Question: What waveform should I use for the reference input?

Answer: For frequencies less than 10MHz you’ll need a minimum slew rate of 21V/uS. The slew rate for frequencies greater than this haven’t been characterized however we can offer some general guidance. The ADF5355 can support reference frequencies as high as 250MHz and up to 600MHz differentially. As frequencies increase the slew rate generally decreases, in other words, what was a square wave at 10MHz looks more sinusoidal at 600MHz unless efforts to preserve the waveform have been taken. The reference input is fed into a buffer amp and then either a multiplier or a counter. As a digital circuit, the counter will operate better with a sharper clocking edge. This means that it may be possible to use a lower drive level when using a square wave than when using a sine wave. A square wave however is rich in odd harmonics while a sinusoidal waveform will include even harmonics as well. This may impact spur performance (refer to the example below).

 

 

 SEE HMC862 DS FOR SQ VS SINE RESIDUAL NOISE PERFORMANCE, DISCUSS POWER IN SQ WAVE VS SINE WAVE. IN GENERAL <1GHz No difference far out

 

 

Question: What is the minimum slew rate that can be used for the Reference input waveform?

Answer: The REFIN circuit can accommodate sine, clipped sine wave and square wave forms however each of these will each provide different phase noise performance levels. Primarily what is being impacted is the residual phase noise of the phase frequency detector (PFD). From a pure phase noise standpoint, the square wave with its high slew rate (sharp clocking edge) will be best. Like all good things though there is a tradeoff. Since the in band (offsets within the loop bandwidth) is most sensitive to our value of ‘N’ to the tune of 20 *Log(N) which in turn is determined by our ‘Comparison’ or FPFD frequency, we typically want our reference frequency to be as high as possible to minimize the integrated phase noise. Unfortunately, retaining this edge becomes more difficult as we increase the frequency. The down side of the square wave is that it’s rich in odd harmonics which can pollute the RF spectrum. The clipped sine wave therefore can sometimes be a better choice and offers a good compromise for noise and spur performance. When spurs are a primary concern and phase noise is secondary or when the comparison frequency is very high a sine wave may be the only option.

 

Question: Does it matter how hard I drive the reference input?

Answer: Typically the best phase noise performance occurs closer to upper end of the drive level, particularly if utilizing a sine wave. You may need to try various power levels particularly if you’re using a sine wave and attempting to optimize for spurs.

 

Question: I’m using a sine wave as opposed to a square wave for my reference; what are the recommended reference input drive level ranges in dBm?

Answer: For single ended into 50Ω, -4dBm to 14dBm; for differential into 100Ω, -7dBm to 6dBm. Be sure to retain AC coupling regardless of mode.

 

Question: What is the reference input impedance?

Answer: This is dependent on the mode being used (Single, Differential) but generally speaking the reference input impedance is high so on the evaluation board a 100Ω resistor is placed across REFinA and REFinB to set the differential input impedance (with DC blocking capacitors between the resistor and the pins 28 & 29 of course).

 

Question: Will driving the input differentially help with spurs or phase noise?

Answer: Driving the reference input differentially may help with spurs, particularly if you’re using a higher reference frequency that will be more sine wave in nature and have even harmonics but it’s unlikely that there will be any impact on harmonics, and phase noise will not improve simply because of the use of differential drive. This assumes that the net drive level and reference frequency remain the same.

 

Question: The datasheet states that “for optimum integer boundary spur (IBS) performance, it is recommended to use the single-ended setting for all references up to 250 MHz (even if using a differential reference signal).  Which mode should I use if IBS performance isn’t a concern for my application?

Answer: In that case the mode should match the input configuration.

 

Question: What is the advantage of the differential input?

 

  1. Allows use of lower drive levels if adequate single ended drive levels aren’t possible. This may be particularly helpful when using a sine wave at lower frequencies.
  2. Common-mode noise rejection and suppression of even harmonics.
  3. Specifically for the ADF5355, it allows higher reference frequencies (Single ended = 250MHz max, Diff = 600MHz Max) which if used will improve in-band phase noise (inside the loop filter) by 20*Log(N). The REFIN circuit can accommodate sine, clipped sine wave and square wave forms however each of these will each provide different (in-band) phase noise performance levels. Primarily what’s being impacted is the residual phase noise of the phase frequency detector (PFD) or the PLL FOM. From a pure phase noise standpoint, the square wave with its high slew rate (sharp clocking edge) will be best. Like all good things though there’s a tradeoff. Since the in-band (noise inside the loop bandwidth) is most sensitive to our value of ‘N’ to the tune of 20 *Log(N) which in turn is determined by our ‘Comparison’ or FPFD frequency, we typically want our reference frequency to be as high as possible to minimize the integrated phase noise. Unfortunately, retaining a sharp clocking edge becomes more difficult as we increase the frequency. The down side of the square wave is that it’s rich in odd harmonics which can pollute the RF spectrum. The clipped sine wave therefore can sometimes be a better choice and offers a good compromise for noise and spur performance. When spurs are the primary concern and phase noise is secondary or when the comparison frequency is very high a sine wave may be the only option.

 

Question: Why can’t REFinB be used with the single ended reference mode?

Answer: Please refer to equivalent circuit in the Reference Input section of the datasheet. This circuit has all of the switches in the “open” state so no particular mode is being illustrated. It’s not possible to open all 4 of the switches as either “Single Ended” or “Differential” must be selected in REG04[DB9=0] placing the circuit into one of the two available states. When set to ‘Single Ended’ switches SW3 and SW4 are open so the differential pair at the bottom of the Reference input equivalent schematic are “off” and SW1 and SW2 are closed. This is a completely different signal path than when operating in differential mode. The single ended path includes an inverter and a buffer amp that can only be accessed from REFinA. If REFinB were to be used some signal does make it through but the desired path is attenuated a series combination of two (2) 2.5kΩ resistors (5kΩ total). Although it actually does seem to work, we recommend users stick to using REFinA when operating single ended.

 

 

RF OUTPUT

Question: Is there a DC offset on RFoutB? I’d like to use CML logic and DC coupling out of the RFoutB port?

Answer: No, RFoutB is AC coupled internally so this won’t be possible

 

Question: I only need to use RFoutB in my application so do I need the pull-up inductors on RFoutA since I plan to power it down?

Answer: The inductors provide a narrow band match for about a 1dB improvement on RFoutA so they aren’t essential and can be eliminated if not needed. There are internal 50Ω pull-up resistors that will continue to provide broadband matching. You may however want to retain a DC block and terminate RFout A into a shunt 50Ω to mitigate any low level RF leakage).

Question: If I don’t install the pull-up inductors on RFoutA will this impact the power level on RFoutB?

Answer: VRF provides the biasing for the output amp and this is what is actually being disabled. Disabling RFoutA should not impact the power level on RFoutB.

 

Question: I have the ADF5355 locked at a particular frequency, when I power up (or down) RFoutA or RFoutB via PDBRF (pin 26) or by enabling / disabling the output buffer on REG6[DB6] for RFoutA or REG6[DB10] through SPI register writes, how long does it take to settle?

 

Answer: There are actually two different questions here.

 

  1. How long does it take the output power to rise or fall?
  2. How long does it take for the phase to settle?

 

The answers to these questions differ by 3 orders of magnitude! The output power settles in nanoseconds, but the phase takes microseconds to settle.

Using a frequency of 825MHz and a logic trigger assumed to be high at 1.2V we measured phase settling to within +/-5 degrees on a high speed scope, the results are shown below.

 

Test

Time

PDBRF On - power settling

33ns

PDBRF Off - power settling

33ns

PDBRF On - phase settling

26us

 

 

SPI On - power settling

67ns

SPI Off - power settling

53ns

SPI On - phase settling

24us

 

 

Question: Does ADI have an RF switch that would be recommended so that RFoutA and RFoutB could be switched in and out as needed?

Answer: If RFoutA is being used single ended then the HMC1118, High Isolation, Silicon SPDT,

Non-Reflective Switch that operates from 9 kHz to 13.0 GHz would be a good choice.

 

SDP-S

 

 

Question: I’m getting an error stating "An SDP system was found, but the daughterboard was not detected. Check the daughterboard is attached to a compatible SDP and press Rescan or Cancel to abort. If your SDP is recently connected, it may be in the process of booting. Wait ~40secs and Rescan." What’s going on?

 

Answer:  The EEPROM should have been programmed during manufacturing and 100% of these ADI evaluation boards are tested so this error would be unusual unless of course you're attempting to use the ADF4355 software to control the ADF5355 in your application or your evaluation board. Of course to do so you will need to have included the EEEPROM on you your board.

If you want to use the Analog Devices evaluation board control software, you will need to program the EEPROM on board. When the software attempts to connect, it looks for a certain ID on the EEPROM. When it finds it, it connects and establishes communication. Below is the process for programming the EEPROM.

  1. Download and install: ftp://ftp.analog.com/pub/evalcd/SDPEEPROMProgrammer.zip
  2. Run the programmer.
  3. Connect SDP board to computer via USB. Connect PLL board to the SDP board.
  4. Copy the settings in the screenshot below and click Write File to EEPROM.

  5. You should get a Programming Successful message. (Sometimes you have to click the button twice to get the message.)

  6. Remove PLL board and replace with next board. Repeat 4 – 6. Don’t disconnect the SDP board or hit the reset button.

 

If you don’t get a Programming Successful message, change the EEPROM Address. It can be anything from 0x50 to 0x57.

 

SETTLING TIME

 

 

Question: Why is the frequency / phase settling time on the ADF5355 so high and how can I measure this using the evaluation board?

Answer: When using the “Write Initialization Sequence” and to a lesser extent “Write Frequency Update Sequence” a number of register writes occur. These register writes set the VCO core, band, and bias. The band-select process that decides which VCO core & band will be used is very reliable, requiring about 1ms. It’s really the bias selection process (ALC) that’s slows things down (~3mS). The best bias value doesn’t change much over frequency (it does however vary depending on the ambient temperature when the ‘Auto-Cal’ routine is run). Once the VCO is configured, a REG 0 write occurs. The REG 0 write actually locks the output. To measure lock time, you should enable the delay (on the ADF4355 GUI Sweep and Hop tab) before R0 and set it to 5mS or so, and then trigger the instrument on the rising-edge of the LE signal on the write to R0.

In the evaluation board control software, these register writes to set up the VCO take several additional milliseconds due to delays in the software, computer, and USB interface. In reality, the register writes will be coming from an FPGA or DSP and will take around 1 µs. Therefore, to really evaluate the full lock time, you need to be at the FPGA / DSP level. The evaluation board control software proves that the concept works; and allows you to measure the settling time after writing to REG 0. This essentially allows you to evaluate whether or not your loop filter is providing the performance needed for your application.

 

Question: I need to achieve a settling time that is much less than 3-4mS, is there anything that I can do?

Answer:  Before we answer this we need to provide a little background. The United States Bureau of Industry and Security manages the export regulations for the United States and publishes a "Commerce Control List" where Category 3 (Electronics), Section A (End Items, Equipment, Accessories, Attachments, Parts, Components and Systems), sub-section "b" refers specifically to microwave and millimeter wave components that are "controlled" when it comes to their export. Herein you'll find the following which must be adhered to:

 

b.11. "Frequency synthesizer" "electronic assemblies" having a "frequency switching time" as specified by any of the following:

   b.11.a. Less than 156 ps;

 

   b.11.b. Less than 100 us for any frequency change exceeding 1.6 GHz within the synthesized frequency range exceeding 4.8 GHz but    not exceeding 10.6 GHz;

 

   b.11.c. Less than 250 us for any frequency change exceeding 550 MHz within the synthesized frequency range exceeding 10.6 GHz but not    exceeding 31.8 GHz;

 

The information that would allow users to achieve sub 3mS settling times could also allow users to achieve settling times which exceed those listed above and is therefore restricted. Please contact Analog Devices to discuss and work through what can be done for your specific application.

 

 

SIMULATION

Question: What software is available to simulate my loop filter and settling time of the ADF5355?

Answer: Use the latest version of ADISimPLL which is available on the ADI website for accurate synthesis of your loop filter and synthesizer performance.

 

 

SPI INTERFACE

Question: Is it possible to control 2 or more devices with a single SPI interface?

Answer: Yes, multiple ADF5355 devices can be accessed using a common SPI interface however the existing ADF4355 software doesn’t allow this level of control since. There are a couple of ways to implement this. The devices typically would share a common SCK (serial clock) line as well as either a common SDI (serial data) or LE (load enable, sometimes referred to as serial enable) but not both. If they share a common LE line then the SDI line would be controlled by a switch routing the programming of the data to the appropriate device during programming. Most of the time however a common SDI line is used then LE is switched to the respective device to complete the programming. The advantage of using a common LE is that the shift register of the part not being programmed isn’t loaded with data that may never be used for that particular device. The advantage of using a common data trace is that that once it is desired to complete the programming the time required to do so is minimal. Most choose the latter option.

 

Question: I’m trying to design and test my hardware that includes the ADF5355 using the SDP-S board by connecting the CLK, DATA, and LE lines.  However the ADI SDP-based evaluation boards have an EEPROM that stores an identification number that the software is checking before it will run.  Is there a way to bypass this EEPROM check or can ADI provide a version of the software that doesn't check the EEPROM?

Answer: Unfortunately there’s no workaround from the software side. The software needs to see the EEPROM. It may be possible to connect the ADF5355 evaluation board to the SDP connector, power up the software and ‘connect’ to the evaluation board then remove the ADF5355 evaluation board. If the software still thinks the evaluation board is there it will continue to write to the registers.

 

Question: According to page 10 of the evaluation board user's guide, there are 1.5k series resistor on the CLK, DATA, and LE lines and then on page 8 those three lines have 1.8k shunt resistors, effectively creating a resistor divider.  The choice of values is perfect for reducing a 3.3V logic signal down to 1.8V, but the ADF5355 on the board uses 3.3V LDO’s.  Are these there in case a user wants to bypass the on-board 3.3V LDOs and run the part off of 1.8V?

 

Answer: The resistor dividers aren’t necessary as the SPI inputs will work with 1.8 V or 3.3 V. The resistor dividers were copied from another design.

 

 

SPURS

Question: When I view the frequency spectrum I’m seeing a “wandering” or “walking” spurs (spurs with a frequency deviation from the carrier changes with time). Are these real and if so what can I do to eliminate them?

Answer: Unfortunately they are real. Over the years, a lot of work by both ADI and by customers has been done to try and understand the root cause and a solution to this problem but nothing definitive has been found. It seems inherent to high-order modulus sigma-delta modulators.

 

In integer N devices these spurs don’t “truly” exist as there’s no delta-sigma modulator (or for fractional devices operating in integer mode, it’s turned off) and just as important – there’s also no frequency error. This is a fractional-N problem. When viewed on a signal analyzer this phenomenon may appear as phase noise ‘breathing’ up and down. This has been witnessed on all early ADI high-order modulus PLLs like the ADF4157, ADF4158, and ADF4159, as well as competitor parts that were released in the same timeframe. The spurs are worse near integer boundaries when the auxiliary modulus (channel spacing) does not evenly divide into the PFD frequency (and possibly at high FRAC2 values even when the auxiliary modulus does evenly divide into the PFD frequency) and when operating in or near the PFD dead-zone.

If you see these in Integer mode the source is most likely your reference, the VCO itself or possibly a gain block. You can try turning each of these blocks off independently to isolate the source.

As a general rule of thumb keeping the PFD frequency as high as possible makes it easier to filter the quantization noise (from the Sigma Delta Modulator) which may help manage spur levels.

We believe the crux of the problem with the “walking spurs” is tied to the auxiliary modulus. The ADF5355 has the additional capability to achieve “zero” frequency error. This is achieved through the use of an additional “auxiliary” fractional word (FRAC2 / MOD2) to eliminate the quantization error that is present when only the primary fractional word (FRAC1 / MOD1 ) is used. In Integer mode the desired lock frequency is perfectly divisible by PFD frequency (no remainder or modulus). Here, the desired lock frequency is perfectly divisible by the PD frequency (no remainder). The 1.6nS anti-backlash pulse provides enough phase offset to maintain good phase detector linearity and minimize the reference spur. In fractional mode, not only do we have the phase detector linearity to deal with (again managed through a 2.6nS anti-backlash pulse and the negative bleed current to maintain PD linearity) but we also have quantization noise from the delta-sigma modulator (DSM). You’ll notice that lower values of FRAC2 (and MOD2) improve the spurious response. This is because the channel spacing is much larger than when FRAC2 & MOD2 values are larger. I’ll try to explain.

 

The fractional term is the remainder after dividing by N. Most (but not all) of this is addressed by the 24 bit fractional word (FRAC1) value. At 122.88MHz there still remains up to 7.32hz of error (122.88MHz / 2^24). To address this, an “auxiliary” fractional word is added for cases when this amount of error is unacceptable. These are the 14 bit, FRAC2 and MOD2 words contained in REG02h. If we can evenly divide the phase detector frequency by some value we can eliminate this “quantization” error. The FRAC2 values and MOD2 values are driven by the “channel spacing” or “step size”. If we choose a step size based on the GCD of the PD frequency and the desired “channel spacing” between integer values and apply a Euclidean algorithm that results in a “0” remainder, the best spurious levels should be achieved. We want to keep the channel spacing (step size) as high as possible which will keep MOD2 as low as possible and if we can eliminate the remainder, FRAC2 = 0 which should provide the best results. If we use 61.44MHz (MOD2=2 and FRAC2 = 0), for instance, these should produce low spur levels. Note MOD2 range is 2 – 16383 and FRAC2 < MOD2.

The reason for the high spurs is primarily the result of a channel spacing that is too small and does not evenly divide into the PD frequency:

So how do the FRAC2 & MOD2 values get to be so high?

  1. Channel spacing / step size is set so narrow that a high MOD2 value (low GCD) occurred
  2. High MOD2 & FRAC2 values were manually entered
  3. Channel spacing value is such that it does not exactly divide into the PD frequency which results in a high value for the FRAC2 register.

 

Generally speaking we recommend that instead of “manually” altering MOD2 & FRAC2 values (when using the ADF4355 evaluation board software use ‘Step size’ (channel spacing) box and verifying that the values produce

  1. A large channel spacing that evenly goes into the PD frequency being used.
  2. This channel spacing should ideally yield FRAC2 = 0 value indicating that there should be no quantization error.  

** If the spacing gets excessively small though it seems that the application hangs up (at least it did for me w/o a device connected)

 

Question: What other types of spurs can I expect to see and what can be done to minimize them?

Answer: Other spurs including Phase Frequency Detector (PFD) spurs, Integer boundary spurs (a special PFD spur), Reference spurs, and random spurs also exist.

Best PFD / IBS spur performance on the ADF5355 is achieved with a charge pump current setting of 0.9mA. There may be isolated cases where this value is decreased (or increased?) slightly (±0.6mA range) and provides slightly better performance for a given application but generally speaking it should remain at 0.9mA.

You may also notice what we refer to as "Direct PFD Harmonics", these are visible in integer mode. They’re harmonics of the PFD signal that aren't modulated by the carrier. As far as we’ve been able to determine they’re the result of circuitry inside the 5355 that square up the PFD frequency which increases the harmonic content. Through various paths these get onto the VCO and the output. If you go to any channel, including any FRAC channel you will see these harmonics.

 

In INT mode the PFD harmonics and the PFD spurs are at the same frequencies. This makes things more confusing. For integer boundaries close to the carrier the PFD spurs are higher and that's what you see. You have a combination of PFD spurs and PFD harmonics at the same frequency. These can be improved by reducing the PFD frequency. Also, the output coupling caps and pull-up inductors can be selected to filter them at high or low frequencies

 

Bleed current should be always be used when operating in fractional mode. REG6 [29] enables negative bleed and REG6[20:13] set the value when operating in fractional mode. If using the ADF4355 GUI, as long as (Auto) “Bleed Current” is checked the negative bleed current multiplier will automatically be selected to keep the bleed current as close as possible to 4 * (Icp / N). By hovering over the check box the algorithm can be seen. There may be cases where specific charge pump values and bleed currents will produce better spurious performance than this setting but in general this setting will produce good first order results based on empirical testing. It should also be noted that there are typically “nulls” that occur depending on the bleed current value. At these “nulls” the spur level may be exceptionally good. The equations that are generally used to calculate bleed currents avoid these nulls as they are subject to process and temperature variation. It’s always a good idea to verify spur performance over temperature on several devices to be sure the setting is robust.

 

If settling time is not an issue, “Gated Bleed” can be enabled (provided digital lock detect is being used which implies that the PFD frequency is <75MHz). This enables “Bleed Current” functionality AFTER lock is declared. Please see the latest datasheet for more information.

Another source of spurious problems is related to what’s commonly referred to as the “Dead Zone”. When the phase error between the VCO and phase detector frequency is very small, phase detector linearity degrades resulting in higher spur levels. To improve the linearity, an anti-backlash pulse is automatically set (1.6nS for integer mode or 2.6nS when operating in fractional mode) to help avoid the dead-zone. This was discussed earlier.

PFD spurs degrade if the reference input frequency is below 250MHz and in ‘Differential’ mode. Generally speaking you want to use the reference mode that matches the input configuration. However, if spurs are critical you’ll want to use ‘Single’ (ended) mode regardless of the configuration as long as your reference frequency is less than 250MHz.

Likewise, if you’re using the output divider, the feedback path in REG6 should be ‘Divided’ for the best spur performance.

Reference input waveform and drive level may impact the spur levels as shown above.

Reference spurs can be optimized with the loop filter and through additional filtering if needed.

Random spurs can come from any number of external sources. Depending on their source and location in the band different approaches can be tried to minimize these. Contact ADI for additional support if these prove problematic.

Finally, board layout, use of linear regulators with high PSRR (avoid switching regulators),and isolating noisy digital circuits (DVDD) and those that switch hard (level shifters, CP) from the reference, VCO and loop filter path will all help you get the best possible spur performance.

 

Question: Is there a way to combine the phenomenal phase noise of the ADF5355 with a PLL that has better FOM to get better close in noise performance or to improve integer boundary spur performance?

Answer: Yes, however there are only certain PLL’s that can be used (ADF4155, HMC704 or similar). Contact ADI for more information.

 

Question: What level of integer boundary spur performance can be achieved by using just the VCO portion of the ADF5355 with an external PLL?

Answer: At close to the minimum spacing between the devices (~8mm) and restricting all peripheral components other than those required for biasing to a 40mm x 80mm region, we have achieved IBS levels of -67dBc and are aware of customers achieving better than -70dBc at 31.25 kHz offsets. This is largely due to the isolation that comes through the physical separation of the devices however proper conditioning of supplies, routing and isolation of the analog, digital and RF signals all play a role in achieving optimal IBS performance.

 

 

SYNCHRONIZING MULTIPLE ADF5355 DEVICES

Question: Can I tie multiple ADF5355 devices onto a single SPI bus and communicate with each one individually?

Answer: Yes. Simply use a separate LE line to each device and switch the respective trace in when needed to load the registers.

 

Question: Can I use multiple ADF5355 devices in parallel to improve phase noise performance?

Answer: Yes, up to a point. This requires a significant amount of board space and increases complexity, particularly when it comes to managing the “calibration” routine that is required to optimize the phase in order to maximize the output power when the frequency span and resolution increases. The theory behind this relies on simply increasing the signal to noise ratio by summing signals at exactly the same frequency and phase at the same moment in time to improve phase noise performance. That being said, the losses associated with recombination efforts eventually negate any improvements. About 4 devices at most is practical. Injection locking and phase noise degradation will occur if the devices and traces aren’t well isolated from one another.

 

 

TEMPERATURE SENSOR

Question: Since multiple bands typically overlap a given frequency, how does the Auto-Calibration routine select the proper band?

Answer: In order to remain phase locked over -40°C to +85°C, a frequency band must be selected that allows the tune voltage to vary enough, relative to the temperature that calibration was performed to retain lock if the temperature were to vary over to the extremes of the operating temperature range . In other words, when operating in Auto-Cal mode, once phase locked, the band can not change in order to retain the phase locked condition as temperature varies. Of course the user can re-calibrate at any time but depending on the temperature this may not result in the best phase noise performance. We know when a part is phase locked, as the temperature decreases, the tuning voltage will need to decrease to retain lock and vice versa if the temperature increases. We also know that we need to stay well away from the CP rails to retain good phase noise performance. If we perform a frequency update using the Auto-Cal routine at +25°C we are close to the midpoint of the operating temperature range so a Vtune voltage that is approximately in the middle or slightly on the lower side is needed. Based on this, a band is selected that meets this Vtune requirement. If we “Re-Calibrate” while operating at -40°C Vtune will need to be closer to the low end of the range while +85°C would require a voltage at the upper end of the range.

 

Question: Why would “Re-Calibrating” at low temperatures degrade phase noise performance?

Answer: The ADF5355 includes circuitry to determine the approximate ambient temperature of the ADF5355. When a frequency is updated with the Auto-Cal routine while the ADF5355 is operating at reduced temperatures, a voltage near the lower end of the tuning range is selected. Because we’re at the lower end of the tuning range, tuning sensitivity (Kv) is higher. This can result in worse phase noise performance than what would be noted if we had performed the frequency update at +25°C where Vtune would be closer to the midpoint and Kv is lower and THEN reduced the temperature. Note that the loop BW also varies proportionally with changes in Kv as well so calibrating at one end of the temperature range will allow a higher percentage of variation in the loop bandwidth vs calibrating at 25°C.

 

 

TEMPERATURE / THERMAL PROBLEMS

Question: The ADF5355 is losing lock on our board as the temperature approaches 60°C; we didn’t see this problem on the evaluation board, why?

Answer: Assuming nothing else in the design has changed (register values, write sequence, components, robust loop filter, etc.) and everything functioned properly on the ADF5355SD1Z evaluation board over temperature, the problem may be tied to an insufficient thermal design in the customer application. This has been the case when “blind” vias were used in the paddle instead of “thru” vias and is due to the increased thermal resistance. Blind vias terminate at some distance though the PCB stack at a dielectric which presents a large thermal resistance. While there is typically a copper layer between the dielectric layers (0.5oz typically), the thin cross section inhibits efficient lateral heat flow to adjacent vias that pass to the bottom of the board. The dielectric layer below (or above) and adjacent to the blind via present an even greater thermal resistance.  

Conversely, the Cu filled thru vias (recommended) within the paddle behave like a heat pipe to efficiently transfer thermal energy to the back side of the board where it can be dissipated through radiation, convection or conduction. Here again the copper fill increases the cross sectional area to improve heat transfer. 

On a related but separate topic, there’s also a comment in the datasheet regarding the use of a lower loss (tangent) material such as Rogers 4350, Rogers 4003 or Rogers 3003 as opposed to FR4 for improved RF performance however there’s another benefit to these materials. Although the impact on thermal performance will be secondary, the Rogers materials mentioned have much better thermal conductivity as well.

Taking the time to maximize the thermal efficiency of your layout / pcb design will reduce the junction temperature of the active devices within the ADF5355 resulting in both robust performance and improved long term reliability. Refer to the figure below which illustrates the difference between blind and thru vias.

 

 

 

VCO BANDS

Question: How wide are the tuning bands in the ADF5355?

Answer: Due to process variation the width of a given “tuning” band will vary on the ADF5355 but 98% are less than 10MHz wide across the 3.4GHz – 6.8GHz tuning range. The actual bands are much wider than this and many bands from each VCO core overlap each other at the VCO core transitions to allow phase lock over the full operating temperature range without switching VCO cores or bands.

 

 

VIBRATION / G-SENSITIVITY

Question: Does Analog Devices have any vibration or G-Sensitivity data on the ADF5355 that can be shared?

Answer: Unfortunately, no; however, the ADF5355 would in general be expected to be relatively immune to most vibration and G-Sensitivity requirements for several reasons. First, as a plastic encapsulated device, the bond wires are secured by the mold compound which significantly improves wire bond reliability and prevents bond wire movement during vibration vs. that of die packaged in a ceramic air cavity for instance. The 5mm^2, leadless chip scale package also minimizes the effects of vibration by minimizing both the mass of the overall device and the distance between the leads and the printed circuit board. The reference and the printed circuit board itself will likely have much more influence on the vibration performance than the device itself.

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