Document created by Vinod Employee on Oct 7, 2016
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Two sets of tables for 3 different RFPLL loop reference frequencies are provided below, one set for FDD operation and the other for TDD operation. The FDD tables enable the VCO temperature compensation with the intent that the user will use longer, more accurate calibration times for the device to remain in operation indefinitely. The TDD tables also have the same VCO temperature compensation and should be used in the FDD independent mode. Note the VCO temperature compensation is completely independent from, and is not shared or slaved with the DCXO temperature compensation in any way.

Tables are provided (attachment)  for 40MHz, 60MHz, and 80MHz reference frequencies. The correct table to use is the one that closest matches the loop FREF for the operating mode. For example, 19.2MHz is a popular reference frequency which could be the device reference frequency applied to the XTAL_N pin. Because the best RFPLL performance is had with the highest possible loop reference frequency up to 80MHz, the RFPLL Reference Blocks would be configured to the X2 mode, resulting in FREF of 38.4MHz. In this case, the 40MHz reference table would be selected. Refer below table for other reference frequencies.





35 - 50 MHz

40 MHz

50 - 70 MHz

60 MHz

70 - 80 MHz

80 MHz


Loop Filter table entries are dependent on reference frequency. The setup parameters pre-configure the VCO for operation based on frequency of operation. In both FDD and TDD temperature compensation is enabled allowing VCO calibration at any temperature (including either of the extremes) and the synthesizer will stay locked over the rated temperature range.


For using TDD LUT’s in FDD independent mode Register 0x23D[D4]  and 0x27D[D4] needs to be set to 1.


These tables are  available in AD9361.c files shared online.

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