AD7768 FAQ - The input seems to be switching faster than the 256 kSPS rate?

Document created by StuartADI Employee on Aug 16, 2016
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The analog input seems to be switching faster than the 256 kSPS output data rate, is this correct?

 

This is a common question for sigma delta ADC architectures like the AD7768.

 

The short answer is "Yes".

 

The Σ-Δ converter is an oversampled architecture, so the actual sampling rate at the analog inputs, that is the rate at which the input sampling switches are opened and closed, is much higher than the ADC output data rate. On the AD7768 the analog input is sampled at twice the modulator clock frequency, fMOD, which is derived from MCLK. The modulator clock frequency is determined by selecting one of three clock divider settings: MCLK/4, MCLK/8, or MCLK/32.

 

For example, when provided with a 32MHz MCLK, and fMOD is MCLK/4 = 8.192 MHz, the analog input switches are switching at a rate of 2 x 8.192 MHz = 16.384 MHz. In this case the data is oversampled by at least 32x, so the maximum output data rate is 8.192 MHz / 32 = 256 kSPS.

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