Known Errata Against ADSP-BF70x Blackfin+ Datasheet

Document created by jobo23 Employee on Jul 25, 2016
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We are currently experiencing problems pushing our known documentation errata to the external site, so this Featured Content blurb is going to highlight the known issues:

 

1> Table 3 (Clock Dividers) on p14 incorrectly indicates that SCLK0 is "Not available on SYS_CLKOUT".  SCLK0 is indeed available as programmed on the part (no divider applied).  The row will be modified to indicate "By 1" in the divider column.

 

2> In Table 28 (Absolute Maximum Ratings) on p59, the Input Voltage specification is only correct for VDD_EXT(Nominal) = 3.3V.  For VDD_EXT(Nominal) = 1.8V, it is not accurate.  The spec is going to be corrected such that the Rating column is modified from "-0.33 V to +3.60 V" to "-0.33 V to VDD_EXT + 0.2 V", which applies to both 3.3V and 1.8V VDD_EXT(Nominal) ranges. As the upper bound now directly references VDD_EXT, the associated footnote 2 on this table must also be reworded from:

 

"Applies only when VDD_EXT is within specifications. When VDD_EXT is outside specifications, the range is VDD_EXT +/- 0.2 V."

to

"Applies only when VDD_EXT is within or below specifications."

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