FAQ :: Embedded Parallel Flash and Flash Controller

Document created by Prashant Employee on May 2, 2016Last modified by Prashant Employee on May 2, 2016
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The ADSP-CM41x processor features ECC-protected embedded parallel flash memory. It consists of up to 1024KB of main memory and up to 8kB of information memory. The main memory is used to store program code and data, while the information memory can be used to store private information, such as security keys.

The flash memory is partitioned into two equal blocks, each containing 512KB of main memory and 4KB of information memory. The main memory is divided into 4KB size pages, which organises as 8 rows of 32 columns each, where each column is of 128-bits data and 16-bit ECC. Each flash block is independently controlled by a dedicated flash controller, which controls code fetches for direct code execution, data reads, erasure and programming of the flash and management of ECC error protection.

For more details, please refer Flash Controller chapter in 'Hardware Reference Manual'.

 

Q1. What is Command mode of flash?

Ans >> In command mode, flash controller accepts the commands to erase the flash page, do the mass erase, program a page, enter or wakeup from sleep mode. The commands can be given by writing to flash controller's memory mapped register, FLC_CMD.

In command mode, the flash controller disables memory mapped accesses to flash by code prefetch unit and DMA port (attempts to access the flash would return Bus_Fault or Hard_Fault).

 

The simple code to configure Flash Controller-0 into Command mode, is as follow. However, it is advised to use device drivers.

 

Similarly the code to return from Command mode to Normal mode is as follow:

 

 

Q2. Is it required to have the code, which programs or erases flash page, in SRAM memory of processor (i.e. not in the flash)? Or can I erase/program a flash page when code executes from another flash page?

Ans >> In order to program or erase a flash page, the flash controller must be in Command mode, where it disables the flash memory accesses. So, it is not possible to have the code in the same flash block where the target block resides. But is it possible to have code in other flash block, since two flash blocks are independently controlled by separate flash controllers. e.g. it is possible to erase/program a page from flash block-0 or mass erase the flash block-0, when code resides in flash block-1; in which case, flash controller-0 must be in Command mode.

 

Simple code to Mass erase the flash block-0:

 

Simple code to erase a page in flash block-0:

 

Simple code to program a page in flash block-0:

The flash can be programmed 64-bits at once.

A program cycle consists of three operations;

- program mode entry: In this step, a row within a particular flash page is activated.

- program mode: In this step, any 64-bit aligned long word within the activated row can be programmed, along with its ECC.

- program mode exit: In this step, the activated row will be deactivated.

 

1. Program entry mode:

 

2. Program mode:

once in program mode, all the words in activated row can be programmed before executing 'program mode exit' step.

 

3. Program mode exit:

 

 

Q3. Whether two flash controllers are completely independent?

>> Both flash controllers operates independently in executing the commands and flash reads requests it receives. However, both flash controllers have common interrupt channels. The Flash Event interrupt and multi-bit ECC error interrupts are shared between two flash controllers. So, in the Interrupt Service Routine (ISR), it is required to check the status bits before proceeding.

 

 

Q4. Is it possible to configure the CGU when CGU programming code is in flash?

>> Yes, the CGU configuration code can be in flash, but make sure to set the flash performance mode correctly, if required.

e.g. after boot, when changing from active mode to set the core clock clock as 240MHz, make sure to change the performance mode to E before programming the CGU. The performance mode can be configured by FLC_PRFCTL.PMODE field.

 

 

Q5. What is the Sleep mode of flash?

>> The flash controller provides a simple sleep mode for flash power-saving purpose. In sleep mode, flash controller ignores flash accesses (requested by code prefetcher and DMA engine) and also commands such as erase, program (It can accept only Sleep Wakeup command). Optionally it is possible to wakeup from sleep mode when the flash accesses are requested.

 

 

Q6. Whether M0 core can access flash?

>> M0 can directly execute code from flash. It can also access data residing in flash.

However, it cannot access memory mapped registers of flash controllers. That means, M0 cannot provide commands such as page erase, mass erase, program, sleep etc.

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