The attached code can be used as a reference to test TWI connections on newly designed board with ADSP SC58x/ ADSP-2158x processors.
The code does the following:
- This code intends to test data transfer between the two TWI modules.
- The TWI is configured in fast mode of operation with one TWI as the master transmitter and the other TWI as the slave receiver.
- The code tests for two types of data patterns:
- Fixed data pattern as 0xAA: This is to check whether the TWI transmit data comes out well.
- Incremental data: This is to make sure that the transmitted data is received properly when it is received by the TWI configured as the slave receiver.
- Appropriate connections should be made externally based on the Tx and Rx choice. For example, if TWI0 is configured as the master transmitter while TWI1 is configured as the slave receiver. In this case, the connections need to be made as follows:
- TWI0_SCL <--> TWI1_SCL
- TWI0_SDA <--> TWI1_SDA
How to modify the code for customized system requirements:
- The existing code uses TWI0 is configured as the master transmitter while TWI1 is configured as the slave receiver.
- The TWI configuration can be modified to any other combination of TWIs.
How to test that the code works?
- To make sure that the TWI signals are coming out on the pins as expected, probe the TWI master clock pins. To make sure that a known data (e.g. 0xAA as byte of the frame in this case) is transferred for easy probing, use the definition “Fixed_data”(See screenshot below).
- For the easy probing of the signals, the SCCB compatible operation has been enabled for TWI and the data transfer counter has been disabled.
The below screenshot shows how the TWI signals should look like
- For a quick sanity check that the TWI slave receiver is able to receive the data as expected, one can look at compare the transmit and receive data (in incremental data format) by looking at the CCES memory window as shown in the screenshot below: