How do I validate SPI on my newly designed board based on ADSP-SC58x/ADSP-2158x processors?

Document created by nithya.koch Employee on Mar 31, 2016
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The attached code can be used as a reference to test SPI connections on newly designed board with ADSP SC58x/ ADSP-2158x processors.

The code does the following:

  • This code intends to test data transfer between the two SPI modules in auto-buffered DMA mode.
  • The SPI is configured in a half-duplex configuration with one SPI as the master transmitter and the other SPI as the slave receiver.
  • The code tests for two types of data patterns:
    • Fixed data pattern as 0xAA: This is to check whether the SPI transmit data comes out well when the SPI MOSI channel is probed using a scope.
    • Random data: This is to make sure that the transmitted data is received properly when it is received by the SPI configured as the slave receiver.
  • Appropriate connections should be made externally based on the TX and RX choice. For example, if SPI0 is configured as the master transmitter while SPI1 is configured as the slave receiver. In this case, the connections need to be made as follows:
    • SPI0_CLK <--> SPI1_CLK
    • SPI0_MOSI <--> SPI1_MOSI
    • SPI0_MISO <--> SPI1_MISO
    • SPI0_SEL (Master) <--> SPI1_SS (Slave)
  • It is recommended to disable cache before executing this code.

How to modify the code for customized system requirements:

  • The existing code provides the flexibility to configure any of the SPIs as the transmitter and the receiver after appropriate changes in the macros.
  • The existing code uses SPI0 is configured as the master transmitter while SPI1 is configured as the slave receiver. The SPI configuration can be modified to use any other combination of SPIs.
  • Various configuration settings for SPI have also been defined in the macros.

How to test that the code works?

  • To make sure that the SPI signals are coming out on the pins as expected, probe the SPI master clock, MOSI pins. To make sure that a known data (e.g. 0xAA as byte of the frame in this case) is transferred for easy probing, use the definition “Fixed_data”(see below screenshot)

The below screenshot shows how the SPI CLK and MOSI signals should look like

  • For a quick sanity check that the SPI slave receiver is able to receive the data as expected, one can look at compare the transmit and receive data (in random data format) by looking at the CCES memory window as shown in the screenshot below:

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