Changing Chip Address in HMC704LP4E

Document created by analog-archivist Employee on Feb 23, 2016Last modified by analog-archivist Employee on Aug 10, 2016
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I have a single PLL system. I would like to control HMC704LP4E in serial open
mode but cannot see how to assign a chip address to the PLL. There are no
hardware pins or registers to set it up. The question concerns the 3 bit chip
address that is embedded in the command word on CLK edges 30-32 of an open mode
write. I cannot find any reference to it in the register information so I don’t
know what the default value is, which would be adequate in my single PLL
system. I cannot find any explanation of how to set up the chip address of my
single PLL and I don’t know what the consequences are of ignoring it.
Presumably the bits have to match what the chip thinks its address is or it
will ignore the command.

 

HMC704LP4E supports two SPI protocols- Open Mode and HMC Mode. This mode
selection occurs after the power-up and POR ( Power-On-Reset ). Approximately
450us after power-up the part will enter SPI mode selection and wait for a
rising edge on either SEN (HMC mode) or SCK (Open mode). 
Mode selection is determined by which SPI signal rising edge occurs first after
power supply voltages are applied (SCK before SEN = Open SPI mode; SEN before
SCK = HMC SPI mode).  SPI mode selection must occur every time the power supply
voltage is applied. PFA :

All HMC PLL’s and PLLVCO’s use 000b as the Chip Address.
The 3-bit chip address by default is 000b. This is fixed and cannot be changed.
All the registers have 24-bit data width + addressing. For example, let’s say
the REG 00h has a default value A7975h can be expanded as 0A 79 75 00 wherein
24 bits-data, 5-bit Reg address, 3 bits- chip address = 32 bits for 32 cycles
of SCK. The default value (000b) shall be adequate for your single PLL system.
There is no way for the user to change the Chip Address. If using more than one
PLL in the system, then separate SEN signals are required to isolate
communication among the different PLLs. (For your reference more on this can be
referred from https://ez.analog.com/docs/DOC-11784 )
Let me know if you have further questions on this. Please find attached the
operation manual with this email for your reference.
PFA :

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