HSC_ADC_EVALCZ_J9 setup-2

Document created by analog-archivist Employee on Feb 23, 2016Last modified by analog-archivist Employee on Feb 23, 2016
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In the user guide, it says J9 is a 6pin connector, can set the FPGA voltage to
1.8V, 2.5V or 3.3V. (The picture grabbed from user guide shows its name is “HSC-
ADC-EVALCZ-DMA”)However in my board , I see it is a 4pin connector, only 2.5V
and 3.3V selection. (My board is “HSC-ADC-EVALCZ    FIFO0501B” , it is
different from the user guide).
And another thing needing your confirmation is, the J9 is used to select the
FPGA IO voltage only, the SPI voltage is 3.3V fixed, am I right?

 

The HSC-ADC-EVALCZ was updated slightly after the datasheet was published to
address some internal debug and Design for Manufacturability improvements.
Customer features were not impacted. The 1.8V wire strap from the original
version was hardwired in metal on the update. So with no jumper on J9 the FPGA
defaults to 1.8V I/O support. 2.5V and 3.3V I/O is selected by adding a
physical jumper to the corresponding location on J9. J9 should be set to match
the DRVDD (output driver) supply voltage used on the ADC brd being evaluated.
You are correct, J9 only controls the I/O voltage of the FPGA used for data
capture via J2/J3. The SPI control voltage is routed directly through the
Cypress USB Controller U3 and onto the ADC eval brd through Connector J1. Our
ADC Eval brds contain circuits that buffer and level shift the SPI control
signals to match the SPI level (typically 1.8V) needed by the ADC.
Here’s an updated image of the current production EVALC capture brd.(see
attachment)

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