High Speed ADCs and HSC-AD-EVALCZ

Document created by analog-archivist Employee on Feb 23, 2016
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Is it possible to customize the HSC-ADC-EVALCZ hardware or the FPGA capture
code ?


 

For users interested in customizing our standard HSC-ADC-EVALCZ hardware and/or
our distributed FPGA capture code we do provide the full hardware BOM,
schematics, and FPGA source code upon request.
ADC model specific HSC-ADC-EVALC FPGA source code is typically posted to our
public FTP site at
ftp://ftp.analog.com/pub/HSSP_SW/fpga/.
The Virtex4 can also be accessed for programming directly via JTAG header J10
using standard ISE development tools available from Xilinx.

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