Clock Distribution Network using HMC parts

Document created by analog-archivist Employee on Feb 23, 2016Last modified by analog-archivist Employee on Aug 10, 2016
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I am in the process of designing a clock distribution network using Hittite
components, and I'd like some advice from the manufacturer. I hope  The core
design consists of the following:

HMC830 or HMC821 as clock source, driving

HMC987 fanout buffer (LVPECL out), driving several

HMC988 programmble clock divider and delay (LVPECL in and out), driving several
HMC1511 ADC's.


Is it recommended for the HMC830/821, producing an RF output, to drive the
HMC987 ? Is there a best practice the can be recommended to do this ?

PART-B (Based on PART-A)
1)      Working from the output levels in the HMC988 datasheet, I assume that
the HMCAD1511 will require OVDD = +3.3V to allow for the large LVPECL swing
into CLKP/N. Is this correct ? The Hittite reference design uses OVDD = +1.8V,
but with a clock input clamped to +1.8V).

2) The HMCAD1511 datasheet does not quote a current consumption number for OVDD
when running from +3V3, which will be required to size the voltage regulator.
Do you have a number that I can work with ?

3) For OVDD = +3.3V, I am assuming that the following will require/allow
signals at +3V3 signaling levels: CS, SDATA, SCLK, RESET and PD. Can you
confirm please.

4) What do I assume for the LVDS common mode outputs when OVDD = +3.3V ? Is it
affected at all ?

5) Is there a specific sequence during power-on, or restrictions that apply
when OVDD is different from the other power supplies to the HMCAD1511 ?
Specifically, does it matter if OVDD precedes AVDD and DVDD ?




Please find attached the recommendation made in the .pdf file.


1. The HMCAD1511 CLK inputs are AC-coupled internally so no additional
configuration changes are needed within the ADC to accept the default LVPECL
(800mVpp Single Ended, 1.6Vppd Differential) Clock signaling output directly
from the HMC988 while operating the HMCAD1511 from the nominal 1.8V OVDD
supply. The standard LVPECL termination scheme shown in your circuit proposal
is correct.

2. The HMCAD1511 OVDD supply domain powers only the Digital CMOS Logic and
Clock Inputs which are inherently low leakage CMOS inputs specified at +/-10uA
max. Even if the OVDD supply needed to be raised to 3.3V for certain legacy
CMOS compatibility I wouldn’t expect the current draw/demand from the OVDD
supply rail to increase very much, if at all, beyond the specified +/-10uA max
per CMOS input pin. As noted above, there’s really no inherent reason why you
should have to increase the HMCAD1511 OVDD supply above the nominal 1.8V level
to interface with the LVPECL Clock coming from the HMC988, even if the HMC988
itself is biased using a 3.3V supply.

3. Yes, the HMCAD1511 Digital CMOS Logic VIH/VIL input compatibility levels
track the OVDD supply. Unless  you specifically need 3.3V Input Logic
compatibility they can/should run OVDD at the nominal 1.8V level.
4. The OVDD supply domain biases only the Digital CMOS/CLK Inputs to
accommodate flexible interfacing to your external 1.7V to 3.6V Control Logic.
The ADC’s Digital LVDS Output Drivers are biased from the nominal 1.8V DVDD
supply domain so they have no direct correlation to the Digital Input OVDD
supply domain.

5. Nothing beyond Power-up sequencing or initialization requirements beyond
those listed on pages 28-29 of the datasheet.