HSC-ADC-EVALB-DC: Software and evaluation system

Document created by analog-archivist Employee on Feb 23, 2016
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We would like to know the end result of the evaluation board. According to
specs there is the capability of SNR, SINAD, SFDR, FFT, frequency and time
domain analysis. Is it true that when in time domain analysis mode the output
data is the actuall captured waveform. Will we be able to view it on the
screen? When in dual channel operation is there a capability of interleaved
mode? I can see that the board supports 133MHz single channel and 266MHz dual
channel but is it interleaved?

 

In time domain analysis modes, the screen can displays a reconstruction of the
data captured by the FIFO evaluation board. This is the actual data from the
evaluation board. Alternatively you can also choose to use the data from the
ADIsimADC application device model for that particular ADC.
Regarding interleaving: ADCs with very high data rates may exceed the
capability of a single buffer memory channel (~133 MSPS). These converters
often demultiplex the data into two channels to reduce the rate required to
capture the data. In these applications, the ADC Analyzer must interleave the
data from both channels to process it as a single channel. The user can
configure the software to process the first sample from Channel 1, the second
from Channel 2, and so on, or vice versa, (see the Troubleshooting section,
page 20 of the attached ADC analyzer user manual for more information on
configuring for interleaved data)

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