QQuestion 1: How is the SPI input for the ADC configured (voltage) ? The input
supply is connected to 1.8V, the control is done with 2.5V.
Question 2: Is this combination allowed ? Will the inputs tolerate the higher
voltage ? The supply of the inputs (OVDD) could also be connected to the VADJ
of the FMC carrier (2.5V).
Question 3: Does the customer has to pay attention on the power on sequencing
of the ADC ?
Question 4: There is no problem with the LVDS connections. But what about the
control interface inputs CSN, SDATA, SCLK and RESET_SPI (pin 2,3,4,5). This
inputs configured for 1.8 V and are connected to 2.5 V outputs! This couldn’t
Question 5: When I use eval board the power – on sequencing is ok. What are
the specifications for the supply sectors when I design my own application?
What happens when the input pins gets voltage before the supply pins.
Especially the control interface. (OVDD sector)
A1. The configuration registers can be accessed through serial interface formed
by SDATA, SCLK and Chip Select (CSN, Active Low – GND connected to via FMC)
Refer Section Serial Interfacing in DS. With Easy Suite S/W, we can directly
handle the SPI and registers I believe but only with SP601 as platform.
2. In the attached document the module is used with a SP601 board, where the
IO-pins are switched to 2.5V. The supply of the ADC is 1.8V (see section 5.1 on
page 6). So again, is this combination (supply 1.8V / Input 2.5V) allowed ?
In principle, the current HMCAD1520 EVB outputs LVDS data referenced to a fixed
1.8V DVDD supply while the Xilinx SP601 capture brd has the LVDS data I/O Banks
0-2 referenced to a fixed 2.5V supply. The differential nature of the LVDS
signaling allows this brd combination to work.
In other words,
I/O cells supply voltage doesn't matter to the LVDS interface as long as Vcm
ranges of the two devices are compatible.
Another check point is the distribution of the power supplies as defined in the
standard FMC – I am assuming this should be same for the customer board. This
is a snapshot from the schematics of the FMC connector from the schematics in
3. Power – on sequencing of the part
The evaluation board itself takes care of the power-up sequencing of the part.
Nothing additional needs to be done on this front. All the supply voltages on
the board come up at the same time.
4. I believe that the HMCAD/SP601 Eval Brd Set-up is taking advantage of
the liberal voltage tolerance/AMR rating on the CMOS Digital Inputs of -0.3V to
+3.9V referenced to GND, not the actual 1.8V OVDD supply rail, even though we
know the CMOS input OVDD supply is fixed at 1.8V on the HMCAD1520 EVB and the
Xilinx SP601 Brd I/O fixed at 2.5V. Please see the AMR ratings below as
specified in the Datasheet.
5. we are not aware of any supply domain sequencing requirements on the
HMCAD1520/11. Likewise it doesn’t appear that any precautions or provisions
exist on the HMCAD eval Brds to address any control over power-up sequencing.
The EVB’s do offer a way to slightly digitally adjust/tweak the core ADC
supplies under FPGA GUI control through the AD5160 Digi-Pot connections but
this is not really related to sequencing.
The datasheet does not include any warnings about supply sequencing so we at
least for now have to assume that there are no sequencing requirements, even if
customers choose to operate from split/different value AVDD, DVDD, and OVDD
supplies…unlike the EVB that has all the supply domains fixed at 1.8V.
Independent of supply sequencing, once the ADC supplies are all up and stable
there is a required digital “start-up initialization” routine that must be
applied to insure the ADC is properly initialized as detailed on d/s pg 9.
Switching between the various device modes of operation
(Channels/Resolutions/etc) also requires additional Initialization procedures
as described on d/s page 35.